- SH2: Added read byte access of TIER register of FRT(3D Lemmings (E)) - SCU: Refactored INTC - SCU: Made DSP and DMAC as separated excutable devices - SCU: Supported irregular(Transfer address is not aligned or transfer count is an odd number) DMA transfers - SCU: Implemented better timing for DMA transfers - SCU: Implemented better synchronization mechanism for DMAC - SCU: Implemented caching of DMA triggers - SCU: Implemented priority for the three DMA levels - SCU: Implemented all status(Access, Interruption, Standby, Operation) of DMA transfers - SCU: Implemented Force-Stop of DMA transfers - SCU: Implemented handling for illegal DMA - SCU: Implemented handling for the Status of Stopped DMA registers - SCU: Added handling for DSTA register - SCU: Added "Cool-down" time for interrupted/Force-Stopped DMA transfers - SCU: Added restrictions for register access - VDP1: Added restrictions for register access - VDP2: Fixed the VBLANK bit of TVSTAT register - CDB: Refactored handling of DATATRNS register - CDB: Added byte access of DATATRNS register(Steam Hearts via SCU DMA) - SYSTEM: Added checking for accessing device registers from slave SH2 - MISC: Refined regular expressions of the CUE parser - MISC: Fixed regular expression bugs of the INI parser