| Project Settings |
|---|
| Project Name | proj_1 | Implementation Name | based |
| Top Module | [auto] | Pipelining | 1 |
| Retiming | 0 | Resource Sharing | 1 |
| Fanout Guide | 1000 | Disable I/O Insertion | 0 |
| Clock Conversion | 1 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
33 |
4 |
0 |
- |
0m:01s |
- |
16.04.2026
21:36:43 |
| (premap) | Complete |
4 |
3 |
0 |
0m:00s |
0m:00s |
145MB |
16.04.2026
21:36:45 |
| (fpga_mapper) | Complete |
9 |
13 |
0 |
0m:05s |
0m:05s |
180MB |
16.04.2026
21:36:51 |
| Multi-srs Generator |
Complete | | | | 0m:00s | | | 16.04.2026
21:36:44 |
| Area Summary |
|---|
|
| Register bits | 1029 |
I/O cells | 69 |
| Block RAMs
(v_ram) | 4 |
DSPs
(dsp_used) | 0 |
| ORCA LUTs
(total_luts) | 947 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| PLL|CLKOP_inferred_clock | 1.0 MHz | 82.9 MHz | 987.942 |
| RP2C02_LITE_LAT_V3|MCLK | 1.0 MHz | 389.0 MHz | 498.715 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 1 / 1 |
| |
|