#Build: Synplify Pro J-2015.03L, Build 030R, Apr 20 2015 #install: C:\lscc\diamond\3.5\synpbase #OS: Windows 7 6.1 #Hostname: A_N_D #Implementation: based Synopsys HDL Compiler, version comp201503p1, Build 058R, built Apr 20 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys Verilog Compiler, version comp201503p1, Build 058R, built Apr 20 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @N: : | : Running Verilog Compiler in System Verilog mode @N: : | : Running Verilog Compiler in Multiple File Compilation Unit mode @I::"C:\lscc\diamond\3.5\synpbase\lib\lucent\machxo2.v" @I::"C:\lscc\diamond\3.5\synpbase\lib\lucent\pmi_def.v" @I::"C:\lscc\diamond\3.5\synpbase\lib\vlog\hypermods.v" @I::"C:\lscc\diamond\3.5\synpbase\lib\vlog\umr_capim.v" @I::"C:\lscc\diamond\3.5\synpbase\lib\vlog\scemi_objects.v" @I::"C:\lscc\diamond\3.5\synpbase\lib\vlog\scemi_pipes.svh" @I::"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v" @I::"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\PLL.v" @I::"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\OAM_RAM.v" @I::"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\OAM2_RAM.v" @I::"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\PALETTE_RAM.v" @I::"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\PALETTE_RGB_TABLE.v" @I::"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\CODER_NTSC_PAL.v" Verilog syntax check successful! Options changed - recompiling Selecting top level module RP2C02_LITE_LAT_V3 @N:CG364 : machxo2.v(1124) | Synthesizing module VLO @N:CG364 : machxo2.v(1730) | Synthesizing module EHXPLLJ @N:CG364 : PLL.v(8) | Synthesizing module PLL @N:CG364 : RP2C02_LITE_LAT_V3.v(488) | Synthesizing module CLK_DIV @N:CG364 : CODER_NTSC_PAL.v(4) | Synthesizing module CODER_NTSC_PAL @N:CG364 : RP2C02_LITE_LAT_V3.v(521) | Synthesizing module REGISTER_SELECT @N:CG364 : RP2C02_LITE_LAT_V3.v(580) | Synthesizing module REG2000_2001 @N:CG364 : RP2C02_LITE_LAT_V3.v(645) | Synthesizing module READBUSMUX @N:CG364 : RP2C02_LITE_LAT_V3.v(684) | Synthesizing module TIMING_GENERATOR @N:CG364 : RP2C02_LITE_LAT_V3.v(897) | Synthesizing module LOCAL_BUS_CONTROL @N:CG364 : RP2C02_LITE_LAT_V3.v(1510) | Synthesizing module SHIFTREG @N:CG364 : RP2C02_LITE_LAT_V3.v(956) | Synthesizing module BG_COLOR @N:CG364 : RP2C02_LITE_LAT_V3.v(1641) | Synthesizing module COUNTER @N:CG364 : RP2C02_LITE_LAT_V3.v(1041) | Synthesizing module PAR_GEN @N:CG364 : RP2C02_LITE_LAT_V3.v(1197) | Synthesizing module OBJ_EVAL @N:CG364 : RP2C02_LITE_LAT_V3.v(1671) | Synthesizing module OAM_COUNTER @N:CG364 : machxo2.v(1120) | Synthesizing module VHI @N:CG364 : machxo2.v(1291) | Synthesizing module DP8KC @N:CG364 : OAM_RAM.v(8) | Synthesizing module OAM_RAM @N:CG364 : OAM2_RAM.v(8) | Synthesizing module OAM2_RAM @N:CG364 : RP2C02_LITE_LAT_V3.v(1250) | Synthesizing module OAM @N:CG364 : RP2C02_LITE_LAT_V3.v(1475) | Synthesizing module FIFO_HPOSCNT @N:CG364 : RP2C02_LITE_LAT_V3.v(1348) | Synthesizing module OBJ_FIFO @N:CG364 : RP2C02_LITE_LAT_V3.v(1537) | Synthesizing module PIX_MUX @N:CG364 : PALETTE_RAM.v(8) | Synthesizing module PALETTE_RAM @N:CG364 : PALETTE_RGB_TABLE.v(8) | Synthesizing module PALETTE_RGB_TABLE @N:CG364 : RP2C02_LITE_LAT_V3.v(1588) | Synthesizing module PALETTE @N:CG364 : RP2C02_LITE_LAT_V3.v(35) | Synthesizing module RP2C02_LITE_LAT_V3 @W:CL159 : RP2C02_LITE_LAT_V3.v(47) | Input VRAMCS is unused @W:CL159 : RP2C02_LITE_LAT_V3.v(48) | Input VRAMA10 is unused @W:CL159 : RP2C02_LITE_LAT_V3.v(1591) | Input nPCLK is unused At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 80MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Mar 31 19:05:46 2026 ###########################################################] Synopsys Netlist Linker, version comp201503p1, Build 058R, built Apr 20 2015 @N: : | Running in 64-bit mode File D:\SRC\PPU_LITE_LATTICE_V3\based\synwork\layer0.srs changed - recompiling @N:NF107 : RP2C02_LITE_LAT_V3.v(35) | Selected library: work cell: RP2C02_LITE_LAT_V3 view verilog as top level @N:NF107 : RP2C02_LITE_LAT_V3.v(35) | Selected library: work cell: RP2C02_LITE_LAT_V3 view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Mar 31 19:05:46 2026 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Mar 31 19:05:46 2026 ###########################################################] Synopsys Netlist Linker, version comp201503p1, Build 058R, built Apr 20 2015 @N: : | Running in 64-bit mode File D:\SRC\PPU_LITE_LATTICE_V3\based\synwork\based_comp.srs changed - recompiling @N:NF107 : RP2C02_LITE_LAT_V3.v(35) | Selected library: work cell: RP2C02_LITE_LAT_V3 view verilog as top level @N:NF107 : RP2C02_LITE_LAT_V3.v(35) | Selected library: work cell: RP2C02_LITE_LAT_V3 view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Mar 31 19:05:48 2026 ###########################################################] Pre-mapping Report Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1176R, Built Apr 20 2015 17:38:44 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03L Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) Linked File: based_scck.rpt Printing clock summary report in "D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\based\based_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 105MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 105MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB) @W:BN132 : rp2c02_lite_lat_v3.v(814) | Removing sequential instance MOD_TIMING_GENERATOR.VC_LATCH, because it is equivalent to instance MOD_TIMING_GENERATOR.RESCL_IN @N:BN362 : rp2c02_lite_lat_v3.v(506) | Removing sequential instance SUBCLK of view:PrimLib.dff(prim) in hierarchy view:work.CLK_DIV(verilog) because there are no references to its outputs @N:BN362 : rp2c02_lite_lat_v3.v(506) | Removing sequential instance SUB[1:0] of view:PrimLib.dff(prim) in hierarchy view:work.CLK_DIV(verilog) because there are no references to its outputs ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 syn_allowed_resources : blockrams=7 set on top level netlist RP2C02_LITE_LAT_V3 Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ------------------------------------------------------------------------------------------- PLL|CLKOP_inferred_clock 121.0 MHz 8.262 inferred Autoconstr_clkgroup_0 RP2C02_LITE_LAT_V3|MCLK 4.2 MHz 240.582 inferred Autoconstr_clkgroup_1 =========================================================================================== @W:MT529 : coder_ntsc_pal.v(108) | Found inferred clock PLL|CLKOP_inferred_clock which controls 1037 sequential elements including MOD_CODER_NTSC_PAL.DIV[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. @W:MT529 : rp2c02_lite_lat_v3.v(506) | Found inferred clock RP2C02_LITE_LAT_V3|MCLK which controls 6 sequential elements including MOD_CLK_DIV.PCLK_P[2:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 79MB peak: 143MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Mar 31 19:05:48 2026 ###########################################################] Map & Optimize Report Synopsys Lattice Technology Mapper, Version maplat, Build 1176R, Built Apr 20 2015 17:38:44 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03L Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) @N:BN362 : rp2c02_lite_lat_v3.v(814) | Removing sequential instance RC in hierarchy view:work.TIMING_GENERATOR(verilog) because there are no references to its outputs @W:BN132 : rp2c02_lite_lat_v3.v(1233) | Removing instance MOD_OBJ_EVAL.OBLATCH[7], because it is equivalent to instance MOD_READBUSMUX.OB_R[7] @W:BN132 : rp2c02_lite_lat_v3.v(1233) | Removing instance MOD_OBJ_EVAL.OBLATCH[6], because it is equivalent to instance MOD_READBUSMUX.OB_R[6] @W:BN132 : rp2c02_lite_lat_v3.v(1233) | Removing instance MOD_OBJ_EVAL.OBLATCH[5], because it is equivalent to instance MOD_READBUSMUX.OB_R[5] @W:BN132 : rp2c02_lite_lat_v3.v(1233) | Removing instance MOD_OBJ_EVAL.OBLATCH[4], because it is equivalent to instance MOD_READBUSMUX.OB_R[4] @W:BN132 : rp2c02_lite_lat_v3.v(1233) | Removing instance MOD_OBJ_EVAL.OBLATCH[3], because it is equivalent to instance MOD_READBUSMUX.OB_R[3] @W:BN132 : rp2c02_lite_lat_v3.v(1233) | Removing instance MOD_OBJ_EVAL.OBLATCH[2], because it is equivalent to instance MOD_READBUSMUX.OB_R[2] @W:BN132 : rp2c02_lite_lat_v3.v(1233) | Removing instance MOD_OBJ_EVAL.OBLATCH[1], because it is equivalent to instance MOD_READBUSMUX.OB_R[1] @W:BN132 : rp2c02_lite_lat_v3.v(1233) | Removing instance MOD_OBJ_EVAL.OBLATCH[0], because it is equivalent to instance MOD_READBUSMUX.OB_R[0] @W:BN132 : rp2c02_lite_lat_v3.v(1567) | Removing instance MOD_PIX_MUX.THO_LATCH[1], because it is equivalent to instance MOD_BG_COLOR.THO1R @W:BN132 : rp2c02_lite_lat_v3.v(1233) | Removing instance MOD_OBJ_EVAL.PDFIFO[1], because it is equivalent to instance MOD_PAR_GEN.TAL_LATCH Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 152MB peak: 153MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 154MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 150MB peak: 154MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 151MB peak: 154MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 154MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 154MB) Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 154MB) Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 171MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:03s -2.62ns 980 / 1031 2 0h:00m:03s -2.62ns 978 / 1031 3 0h:00m:03s -2.62ns 979 / 1031 4 0h:00m:03s -2.62ns 979 / 1031 5 0h:00m:03s -2.62ns 979 / 1031 @N:FX271 : rp2c02_lite_lat_v3.v(814) | Instance "MOD_TIMING_GENERATOR.V[0]" with 16 loads replicated 1 times to improve timing @N:FX271 : rp2c02_lite_lat_v3.v(814) | Instance "MOD_TIMING_GENERATOR.V[1]" with 13 loads replicated 1 times to improve timing @N:FX271 : rp2c02_lite_lat_v3.v(814) | Instance "MOD_TIMING_GENERATOR.V[2]" with 13 loads replicated 1 times to improve timing @N:FX271 : rp2c02_lite_lat_v3.v(814) | Instance "MOD_TIMING_GENERATOR.V[3]" with 13 loads replicated 1 times to improve timing @N:FX271 : rp2c02_lite_lat_v3.v(814) | Instance "MOD_TIMING_GENERATOR.V[4]" with 10 loads replicated 1 times to improve timing @N:FX271 : rp2c02_lite_lat_v3.v(1430) | Instance "MOD_OBJ_FIFO.SH3" with 4 loads replicated 1 times to improve timing @N:FX271 : | Instance "G_33" with 2 loads replicated 1 times to improve timing Timing driven replication report Added 6 Registers via timing driven replication Added 2 LUTs via timing driven replication 6 0h:00m:03s -2.02ns 993 / 1037 7 0h:00m:03s -2.02ns 994 / 1037 8 0h:00m:03s -2.02ns 993 / 1037 9 0h:00m:03s -2.02ns 994 / 1037 10 0h:00m:03s -2.02ns 993 / 1037 11 0h:00m:04s -2.02ns 996 / 1037 12 0h:00m:04s -2.02ns 997 / 1037 13 0h:00m:04s -2.02ns 996 / 1037 14 0h:00m:04s -2.02ns 997 / 1037 15 0h:00m:04s -2.02ns 996 / 1037 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 169MB peak: 171MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.V_fast_4_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.V_fast_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.V_fast_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.V_fast_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.V_fast_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1567) | Boundary register MOD_PIX_MUX.STEP3_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1567) | Boundary register MOD_PIX_MUX.STEP3_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1567) | Boundary register MOD_PIX_MUX.STEP3_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1567) | Boundary register MOD_PIX_MUX.STEP3_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1627) | Boundary register MOD_PALETTE.PIX_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1627) | Boundary register MOD_PALETTE.PIX_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1627) | Boundary register MOD_PALETTE.PIX_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1627) | Boundary register MOD_PALETTE.PIX_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1430) | Boundary register MOD_OBJ_FIFO.SEL_LATCH_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1430) | Boundary register MOD_OBJ_FIFO.SEL_LATCH_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1430) | Boundary register MOD_OBJ_FIFO.SEL_LATCH_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1430) | Boundary register MOD_OBJ_FIFO.SEL_LATCH_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1497) | Boundary register MOD_OBJ_FIFO.HPOSCNT7.EN.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1497) | Boundary register MOD_OBJ_FIFO.HPOSCNT6.EN.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1497) | Boundary register MOD_OBJ_FIFO.HPOSCNT5.EN.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1497) | Boundary register MOD_OBJ_FIFO.HPOSCNT4.EN.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1497) | Boundary register MOD_OBJ_FIFO.HPOSCNT3.EN.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1497) | Boundary register MOD_OBJ_FIFO.HPOSCNT2.EN.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1497) | Boundary register MOD_OBJ_FIFO.HPOSCNT1.EN.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1497) | Boundary register MOD_OBJ_FIFO.HPOSCNT0.EN.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1319) | Boundary register MOD_OAM.OB_7_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1319) | Boundary register MOD_OAM.OB_6_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1319) | Boundary register MOD_OAM.OB_5_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1319) | Boundary register MOD_OAM.OB_4_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1319) | Boundary register MOD_OAM.OB_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1319) | Boundary register MOD_OAM.OB_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1319) | Boundary register MOD_OAM.OB_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1319) | Boundary register MOD_OAM.OB_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1693) | Boundary register MOD_OAM.OAMCNT.CNT_5_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1693) | Boundary register MOD_OAM.OAMCNT.CNT_4_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1693) | Boundary register MOD_OAM.OAMCNT.CNT_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1693) | Boundary register MOD_OAM.OAMCNT.CNT_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1693) | Boundary register MOD_OAM.OAMCNT.CNT_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.H_8_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.H_7_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.H_6_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.H_5_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.H_4_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.H_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.H_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.H_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.H_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.V_8_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.V_7_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.V_6_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.V_5_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.V_4_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.V_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.V_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.V_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(814) | Boundary register MOD_TIMING_GENERATOR.V_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 169MB peak: 171MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 6 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 1036 clock pin(s) of sequential element(s) 0 instances converted, 1036 sequential instances remain driven by gated/generated clocks ============================== Non-Gated/Non-Generated Clocks =============================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------------- ClockId0002 MCLK port 6 MOD_CLK_DIV.PCLK_N[1] ============================================================================================= ==================================================================================================== Gated/Generated Clocks ===================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 MOD_PLL.PLLInst_0 EHXPLLJ 1036 MOD_READBUSMUX.Do[7] Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements ================================================================================================================================================================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 132MB peak: 171MB) Writing Analyst data base D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\based\synwork\based_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 168MB peak: 171MB) Writing EDIF Netlist and constraint files J-2015.03L @N:BW106 : | Synplicity Constraint File capacitance units using default value of 1pF Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 172MB peak: 174MB) Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 171MB peak: 174MB) @W:MT246 : pll.v(64) | Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock RP2C02_LITE_LAT_V3|MCLK with period 1.54ns. Please declare a user-defined clock on object "p:MCLK" @W:MT420 : | Found inferred clock PLL|CLKOP_inferred_clock with period 6.24ns. Please declare a user-defined clock on object "n:MOD_PLL.CLKOP" @S |##### START OF TIMING REPORT #####[ # Timing Report written on Tue Mar 31 19:05:54 2026 # Top view: RP2C02_LITE_LAT_V3 Requested Frequency: 160.2 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: -1.128 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------------- PLL|CLKOP_inferred_clock 160.2 MHz 135.6 MHz 6.244 7.372 -1.128 inferred Autoconstr_clkgroup_0 RP2C02_LITE_LAT_V3|MCLK 650.8 MHz 412.1 MHz 1.537 2.427 -0.445 inferred Autoconstr_clkgroup_1 ================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------------------------------- PLL|CLKOP_inferred_clock PLL|CLKOP_inferred_clock | 6.244 -1.128 | No paths - | No paths - | No paths - RP2C02_LITE_LAT_V3|MCLK PLL|CLKOP_inferred_clock | Diff grp - | No paths - | No paths - | Diff grp - RP2C02_LITE_LAT_V3|MCLK RP2C02_LITE_LAT_V3|MCLK | 1.537 -0.271 | No paths - | 0.768 -0.445 | No paths - ============================================================================================================================================ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: PLL|CLKOP_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------- MOD_READBUSMUX.OB_R[0] PLL|CLKOP_inferred_clock FD1P3AX Q OB_R[0] 1.108 -1.128 MOD_TIMING_GENERATOR.V_fast[0] PLL|CLKOP_inferred_clock FD1P3IX Q V_fast[0] 0.972 -0.992 MOD_READBUSMUX.OB_R[1] PLL|CLKOP_inferred_clock FD1P3AX Q OB_R[1] 1.044 -0.921 MOD_READBUSMUX.OB_R[2] PLL|CLKOP_inferred_clock FD1P3AX Q OB_R[2] 1.044 -0.921 MOD_TIMING_GENERATOR.V_fast[1] PLL|CLKOP_inferred_clock FD1P3IX Q V_fast[1] 0.972 -0.850 MOD_TIMING_GENERATOR.V_fast[2] PLL|CLKOP_inferred_clock FD1P3IX Q V_fast[2] 0.972 -0.850 MOD_PAR_GEN.PAD[9] PLL|CLKOP_inferred_clock FD1P3AX Q PA9_c 1.108 -0.342 MOD_PAR_GEN.PAD[10] PLL|CLKOP_inferred_clock FD1P3AX Q PA10_c 1.108 -0.342 MOD_PAR_GEN.PAD[11] PLL|CLKOP_inferred_clock FD1P3AX Q PA11_c 1.108 -0.342 MOD_LOCAL_BUS_CONTROL.BLNK_LATCH PLL|CLKOP_inferred_clock FD1P3AX Q BLNK_LATCH 1.044 -0.278 ======================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------- MOD_OAM.OMFG_LATCH PLL|CLKOP_inferred_clock FD1P3AX D un1_OMFG_i 6.138 -1.128 MOD_OAM.OMV_LATCH PLL|CLKOP_inferred_clock FD1P3AX D OMV 6.138 -1.128 MOD_OAM.OSTEP[2] PLL|CLKOP_inferred_clock FD1P3AX D un1_OMFG 6.138 -1.128 MOD_OAM.OAMCNT.CNT1[0] PLL|CLKOP_inferred_clock FD1P3AX D CNT1_2[0] 6.333 -1.102 MOD_OAM.OAMCNT.CNT1[1] PLL|CLKOP_inferred_clock FD1P3AX D CNT1_2[1] 6.333 -1.102 MOD_OAM.OAMCNT.CNT1[2] PLL|CLKOP_inferred_clock FD1P3AX D CNT1_2[2] 6.333 -1.102 MOD_OAM.OAMCNT.CNT1[3] PLL|CLKOP_inferred_clock FD1P3AX D CNT1_2[3] 6.333 -1.102 MOD_OAM.OAMCNT.CNT1[4] PLL|CLKOP_inferred_clock FD1P3AX D CNT1_2[4] 6.333 -1.102 MOD_OAM.OAMCNT.CNT1[5] PLL|CLKOP_inferred_clock FD1P3AX D CNT1_2[5] 6.333 -1.102 MOD_OAM.OAMCNT.CNT1[6] PLL|CLKOP_inferred_clock FD1P3AX D CNT1_2[6] 6.333 -1.102 ============================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 6.244 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.138 - Propagation time: 7.266 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.128 Number of logic level(s): 6 Starting point: MOD_READBUSMUX.OB_R[0] / Q Ending point: MOD_OAM.OMFG_LATCH / D The start point is clocked by PLL|CLKOP_inferred_clock [rising] on pin CK The end point is clocked by PLL|CLKOP_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- MOD_READBUSMUX.OB_R[0] FD1P3AX Q Out 1.108 1.108 - OB_R[0] Net - - - - 3 MOD_OBJ_EVAL.OVS_cry_0_0 CCU2D B1 In 0.000 1.108 - MOD_OBJ_EVAL.OVS_cry_0_0 CCU2D COUT Out 1.545 2.652 - OVS_cry_0 Net - - - - 1 MOD_OBJ_EVAL.OVS_cry_1_0 CCU2D CIN In 0.000 2.652 - MOD_OBJ_EVAL.OVS_cry_1_0 CCU2D COUT Out 0.143 2.795 - OVS_cry_2 Net - - - - 1 MOD_OBJ_EVAL.OVS_cry_3_0 CCU2D CIN In 0.000 2.795 - MOD_OBJ_EVAL.OVS_cry_3_0 CCU2D S0 Out 1.725 4.520 - OV[3] Net - - - - 4 MOD_OBJ_EVAL.OVS_cry_3_0_RNIF7I04 ORCALUT4 D In 0.000 4.520 - MOD_OBJ_EVAL.OVS_cry_3_0_RNIF7I04 ORCALUT4 Z Out 1.017 5.537 - OVS_cry_3_0_RNIF7I04 Net - - - - 1 MOD_OBJ_EVAL.OVS_cry_5_0_RNIR5NP4 ORCALUT4 D In 0.000 5.537 - MOD_OBJ_EVAL.OVS_cry_5_0_RNIR5NP4 ORCALUT4 Z Out 1.281 6.818 - un1_DO_COPY Net - - - - 11 MOD_OBJ_EVAL.CLATCH_RNIM0D86[5] ORCALUT4 D In 0.000 6.818 - MOD_OBJ_EVAL.CLATCH_RNIM0D86[5] ORCALUT4 Z Out 0.449 7.266 - un1_OMFG_i Net - - - - 1 MOD_OAM.OMFG_LATCH FD1P3AX D In 0.000 7.266 - ==================================================================================================== Path information for path number 2: Requested Period: 6.244 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.138 - Propagation time: 7.266 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.128 Number of logic level(s): 6 Starting point: MOD_READBUSMUX.OB_R[0] / Q Ending point: MOD_OAM.OSTEP[2] / D The start point is clocked by PLL|CLKOP_inferred_clock [rising] on pin CK The end point is clocked by PLL|CLKOP_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- MOD_READBUSMUX.OB_R[0] FD1P3AX Q Out 1.108 1.108 - OB_R[0] Net - - - - 3 MOD_OBJ_EVAL.OVS_cry_0_0 CCU2D B1 In 0.000 1.108 - MOD_OBJ_EVAL.OVS_cry_0_0 CCU2D COUT Out 1.545 2.652 - OVS_cry_0 Net - - - - 1 MOD_OBJ_EVAL.OVS_cry_1_0 CCU2D CIN In 0.000 2.652 - MOD_OBJ_EVAL.OVS_cry_1_0 CCU2D COUT Out 0.143 2.795 - OVS_cry_2 Net - - - - 1 MOD_OBJ_EVAL.OVS_cry_3_0 CCU2D CIN In 0.000 2.795 - MOD_OBJ_EVAL.OVS_cry_3_0 CCU2D S0 Out 1.725 4.520 - OV[3] Net - - - - 4 MOD_OBJ_EVAL.OVS_cry_3_0_RNIF7I04 ORCALUT4 D In 0.000 4.520 - MOD_OBJ_EVAL.OVS_cry_3_0_RNIF7I04 ORCALUT4 Z Out 1.017 5.537 - OVS_cry_3_0_RNIF7I04 Net - - - - 1 MOD_OBJ_EVAL.OVS_cry_5_0_RNIR5NP4 ORCALUT4 D In 0.000 5.537 - MOD_OBJ_EVAL.OVS_cry_5_0_RNIR5NP4 ORCALUT4 Z Out 1.281 6.818 - un1_DO_COPY Net - - - - 11 MOD_OBJ_EVAL.un1_OMFG ORCALUT4 D In 0.000 6.818 - MOD_OBJ_EVAL.un1_OMFG ORCALUT4 Z Out 0.449 7.266 - un1_OMFG Net - - - - 1 MOD_OAM.OSTEP[2] FD1P3AX D In 0.000 7.266 - ==================================================================================================== Path information for path number 3: Requested Period: 6.244 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.138 - Propagation time: 7.266 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.128 Number of logic level(s): 6 Starting point: MOD_READBUSMUX.OB_R[0] / Q Ending point: MOD_OAM.OMV_LATCH / D The start point is clocked by PLL|CLKOP_inferred_clock [rising] on pin CK The end point is clocked by PLL|CLKOP_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- MOD_READBUSMUX.OB_R[0] FD1P3AX Q Out 1.108 1.108 - OB_R[0] Net - - - - 3 MOD_OBJ_EVAL.OVS_cry_0_0 CCU2D B1 In 0.000 1.108 - MOD_OBJ_EVAL.OVS_cry_0_0 CCU2D COUT Out 1.545 2.652 - OVS_cry_0 Net - - - - 1 MOD_OBJ_EVAL.OVS_cry_1_0 CCU2D CIN In 0.000 2.652 - MOD_OBJ_EVAL.OVS_cry_1_0 CCU2D COUT Out 0.143 2.795 - OVS_cry_2 Net - - - - 1 MOD_OBJ_EVAL.OVS_cry_3_0 CCU2D CIN In 0.000 2.795 - MOD_OBJ_EVAL.OVS_cry_3_0 CCU2D S0 Out 1.725 4.520 - OV[3] Net - - - - 4 MOD_OBJ_EVAL.OVS_cry_3_0_RNIF7I04 ORCALUT4 D In 0.000 4.520 - MOD_OBJ_EVAL.OVS_cry_3_0_RNIF7I04 ORCALUT4 Z Out 1.017 5.537 - OVS_cry_3_0_RNIF7I04 Net - - - - 1 MOD_OBJ_EVAL.OVS_cry_5_0_RNIR5NP4 ORCALUT4 D In 0.000 5.537 - MOD_OBJ_EVAL.OVS_cry_5_0_RNIR5NP4 ORCALUT4 Z Out 1.281 6.818 - un1_DO_COPY Net - - - - 11 MOD_OAM.OAMCNT.C_OUT ORCALUT4 D In 0.000 6.818 - MOD_OAM.OAMCNT.C_OUT ORCALUT4 Z Out 0.449 7.266 - OMV Net - - - - 1 MOD_OAM.OMV_LATCH FD1P3AX D In 0.000 7.266 - ==================================================================================================== Path information for path number 4: Requested Period: 6.244 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.333 - Propagation time: 7.434 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.102 Number of logic level(s): 6 Starting point: MOD_READBUSMUX.OB_R[0] / Q Ending point: MOD_OAM.OAMCNT.CNT1[0] / D The start point is clocked by PLL|CLKOP_inferred_clock [rising] on pin CK The end point is clocked by PLL|CLKOP_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------- MOD_READBUSMUX.OB_R[0] FD1P3AX Q Out 1.108 1.108 - OB_R[0] Net - - - - 3 MOD_OBJ_EVAL.OVS_cry_0_0 CCU2D B1 In 0.000 1.108 - MOD_OBJ_EVAL.OVS_cry_0_0 CCU2D COUT Out 1.545 2.652 - OVS_cry_0 Net - - - - 1 MOD_OBJ_EVAL.OVS_cry_1_0 CCU2D CIN In 0.000 2.652 - MOD_OBJ_EVAL.OVS_cry_1_0 CCU2D COUT Out 0.143 2.795 - OVS_cry_2 Net - - - - 1 MOD_OBJ_EVAL.OVS_cry_3_0 CCU2D CIN In 0.000 2.795 - MOD_OBJ_EVAL.OVS_cry_3_0 CCU2D S0 Out 1.725 4.520 - OV[3] Net - - - - 4 MOD_OBJ_EVAL.OVS_cry_3_0_RNIF7I04 ORCALUT4 D In 0.000 4.520 - MOD_OBJ_EVAL.OVS_cry_3_0_RNIF7I04 ORCALUT4 Z Out 1.017 5.537 - OVS_cry_3_0_RNIF7I04 Net - - - - 1 MOD_OBJ_EVAL.OVS_cry_5_0_RNIR5NP4 ORCALUT4 D In 0.000 5.537 - MOD_OBJ_EVAL.OVS_cry_5_0_RNIR5NP4 ORCALUT4 Z Out 1.281 6.818 - un1_DO_COPY Net - - - - 11 MOD_OAM.OAMCNT.CNT1_2_mb_mb_mb_mb_mb_mb[0] ORCALUT4 C In 0.000 6.818 - MOD_OAM.OAMCNT.CNT1_2_mb_mb_mb_mb_mb_mb[0] ORCALUT4 Z Out 0.617 7.434 - CNT1_2[0] Net - - - - 1 MOD_OAM.OAMCNT.CNT1[0] FD1P3AX D In 0.000 7.434 - ============================================================================================================= Path information for path number 5: Requested Period: 6.244 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.333 - Propagation time: 7.434 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.102 Number of logic level(s): 6 Starting point: MOD_READBUSMUX.OB_R[0] / Q Ending point: MOD_OAM.OAMCNT.CNT1[6] / D The start point is clocked by PLL|CLKOP_inferred_clock [rising] on pin CK The end point is clocked by PLL|CLKOP_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- MOD_READBUSMUX.OB_R[0] FD1P3AX Q Out 1.108 1.108 - OB_R[0] Net - - - - 3 MOD_OBJ_EVAL.OVS_cry_0_0 CCU2D B1 In 0.000 1.108 - MOD_OBJ_EVAL.OVS_cry_0_0 CCU2D COUT Out 1.545 2.652 - OVS_cry_0 Net - - - - 1 MOD_OBJ_EVAL.OVS_cry_1_0 CCU2D CIN In 0.000 2.652 - MOD_OBJ_EVAL.OVS_cry_1_0 CCU2D COUT Out 0.143 2.795 - OVS_cry_2 Net - - - - 1 MOD_OBJ_EVAL.OVS_cry_3_0 CCU2D CIN In 0.000 2.795 - MOD_OBJ_EVAL.OVS_cry_3_0 CCU2D S0 Out 1.725 4.520 - OV[3] Net - - - - 4 MOD_OBJ_EVAL.OVS_cry_3_0_RNIF7I04 ORCALUT4 D In 0.000 4.520 - MOD_OBJ_EVAL.OVS_cry_3_0_RNIF7I04 ORCALUT4 Z Out 1.017 5.537 - OVS_cry_3_0_RNIF7I04 Net - - - - 1 MOD_OBJ_EVAL.OVS_cry_5_0_RNIR5NP4 ORCALUT4 D In 0.000 5.537 - MOD_OBJ_EVAL.OVS_cry_5_0_RNIR5NP4 ORCALUT4 Z Out 1.281 6.818 - un1_DO_COPY Net - - - - 11 MOD_OAM.OAMCNT.CNT1_2[6] ORCALUT4 D In 0.000 6.818 - MOD_OAM.OAMCNT.CNT1_2[6] ORCALUT4 Z Out 0.617 7.434 - CNT1_2[6] Net - - - - 1 MOD_OAM.OAMCNT.CNT1[6] FD1P3AX D In 0.000 7.434 - ==================================================================================================== ==================================== Detailed Report for Clock: RP2C02_LITE_LAT_V3|MCLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------- MOD_CLK_DIV.PCLK_P[1] RP2C02_LITE_LAT_V3|MCLK FD1S3AX Q PCLK_P[1] 1.108 -0.445 MOD_CLK_DIV.PCLK_N[1] RP2C02_LITE_LAT_V3|MCLK FD1S3AX Q PCLK_N[1] 1.280 -0.271 MOD_CLK_DIV.PCLK_P[2] RP2C02_LITE_LAT_V3|MCLK FD1S3AX Q PCLK_P[2] 1.280 -0.271 MOD_CLK_DIV.PCLK_N[0] RP2C02_LITE_LAT_V3|MCLK FD1S3AX Q PCLK_N[0] 0.972 0.459 MOD_CLK_DIV.PCLK_P[0] RP2C02_LITE_LAT_V3|MCLK FD1S3AX Q PCLK_P[0] 0.972 0.459 ========================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------- MOD_CLK_DIV.PCLK_P[3] RP2C02_LITE_LAT_V3|MCLK FD1S3AX D PCLK_P[1] 0.663 -0.445 MOD_CLK_DIV.PCLK_N[0] RP2C02_LITE_LAT_V3|MCLK FD1S3AX D un2_PCLK_N_i 1.625 -0.271 MOD_CLK_DIV.PCLK_P[0] RP2C02_LITE_LAT_V3|MCLK FD1S3AX D un2_PCLK_P_i 1.625 -0.271 MOD_CLK_DIV.PCLK_P[2] RP2C02_LITE_LAT_V3|MCLK FD1S3AX D PCLK_P[1] 1.431 0.323 MOD_CLK_DIV.PCLK_N[1] RP2C02_LITE_LAT_V3|MCLK FD1S3AX D PCLK_N[0] 1.431 0.459 MOD_CLK_DIV.PCLK_P[1] RP2C02_LITE_LAT_V3|MCLK FD1S3AX D PCLK_P[0] 1.431 0.459 ============================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 0.768 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 0.663 - Propagation time: 1.108 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.445 Number of logic level(s): 0 Starting point: MOD_CLK_DIV.PCLK_P[1] / Q Ending point: MOD_CLK_DIV.PCLK_P[3] / D The start point is clocked by RP2C02_LITE_LAT_V3|MCLK [rising] on pin CK The end point is clocked by RP2C02_LITE_LAT_V3|MCLK [falling] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- MOD_CLK_DIV.PCLK_P[1] FD1S3AX Q Out 1.108 1.108 - PCLK_P[1] Net - - - - 3 MOD_CLK_DIV.PCLK_P[3] FD1S3AX D In 0.000 1.108 - ======================================================================================= Path information for path number 2: Requested Period: 1.537 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) = Required time: 1.625 - Propagation time: 1.897 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.271 Number of logic level(s): 1 Starting point: MOD_CLK_DIV.PCLK_N[1] / Q Ending point: MOD_CLK_DIV.PCLK_N[0] / D The start point is clocked by RP2C02_LITE_LAT_V3|MCLK [rising] on pin CK The end point is clocked by RP2C02_LITE_LAT_V3|MCLK [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- MOD_CLK_DIV.PCLK_N[1] FD1S3AX Q Out 1.280 1.280 - PCLK_N[1] Net - - - - 20 MOD_CLK_DIV.PCLK_N_RNO[0] ORCALUT4 A In 0.000 1.280 - MOD_CLK_DIV.PCLK_N_RNO[0] ORCALUT4 Z Out 0.617 1.897 - un2_PCLK_N_i Net - - - - 1 MOD_CLK_DIV.PCLK_N[0] FD1S3AX D In 0.000 1.897 - ============================================================================================ Path information for path number 3: Requested Period: 1.537 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) = Required time: 1.625 - Propagation time: 1.897 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.271 Number of logic level(s): 1 Starting point: MOD_CLK_DIV.PCLK_P[2] / Q Ending point: MOD_CLK_DIV.PCLK_P[0] / D The start point is clocked by RP2C02_LITE_LAT_V3|MCLK [rising] on pin CK The end point is clocked by RP2C02_LITE_LAT_V3|MCLK [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- MOD_CLK_DIV.PCLK_P[2] FD1S3AX Q Out 1.280 1.280 - PCLK_P[2] Net - - - - 20 MOD_CLK_DIV.PCLK_P_RNO[0] ORCALUT4 A In 0.000 1.280 - MOD_CLK_DIV.PCLK_P_RNO[0] ORCALUT4 Z Out 0.617 1.897 - un2_PCLK_P_i Net - - - - 1 MOD_CLK_DIV.PCLK_P[0] FD1S3AX D In 0.000 1.897 - ============================================================================================ Path information for path number 4: Requested Period: 1.537 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) = Required time: 1.625 - Propagation time: 1.725 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.099 Number of logic level(s): 1 Starting point: MOD_CLK_DIV.PCLK_P[1] / Q Ending point: MOD_CLK_DIV.PCLK_P[0] / D The start point is clocked by RP2C02_LITE_LAT_V3|MCLK [rising] on pin CK The end point is clocked by RP2C02_LITE_LAT_V3|MCLK [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- MOD_CLK_DIV.PCLK_P[1] FD1S3AX Q Out 1.108 1.108 - PCLK_P[1] Net - - - - 3 MOD_CLK_DIV.PCLK_P_RNO[0] ORCALUT4 B In 0.000 1.108 - MOD_CLK_DIV.PCLK_P_RNO[0] ORCALUT4 Z Out 0.617 1.725 - un2_PCLK_P_i Net - - - - 1 MOD_CLK_DIV.PCLK_P[0] FD1S3AX D In 0.000 1.725 - ============================================================================================ Path information for path number 5: Requested Period: 1.537 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 1.431 - Propagation time: 1.108 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.323 Number of logic level(s): 0 Starting point: MOD_CLK_DIV.PCLK_P[1] / Q Ending point: MOD_CLK_DIV.PCLK_P[2] / D The start point is clocked by RP2C02_LITE_LAT_V3|MCLK [rising] on pin CK The end point is clocked by RP2C02_LITE_LAT_V3|MCLK [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- MOD_CLK_DIV.PCLK_P[1] FD1S3AX Q Out 1.108 1.108 - PCLK_P[1] Net - - - - 3 MOD_CLK_DIV.PCLK_P[2] FD1S3AX D In 0.000 1.108 - ======================================================================================= ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 171MB peak: 174MB) Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 171MB peak: 174MB) --------------------------------------- Resource Usage Report Part: lcmxo2_1200hc-4 Register bits: 1037 of 1280 (81%) PIC Latch: 0 I/O cells: 69 Block Rams : 4 of 7 (57%) Details: BB: 16 CCU2D: 5 DP8KC: 4 EHXPLLJ: 1 FD1P3AX: 876 FD1P3DX: 10 FD1P3IX: 48 FD1P3JX: 10 FD1S3AX: 47 FD1S3IX: 25 GSR: 1 IB: 11 IFS1P3DX: 21 INV: 43 L6MUX21: 5 OB: 39 OBZ: 3 ORCALUT4: 958 PFUMX: 16 PUR: 1 VHI: 70 VLO: 62 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 57MB peak: 174MB) Process took 0h:00m:06s realtime, 0h:00m:06s cputime # Tue Mar 31 19:05:55 2026 ###########################################################]