#Build: Synplify Pro J-2015.03L, Build 030R, Apr 20 2015 #install: C:\lscc\diamond\3.5\synpbase #OS: Windows 8 6.2 #Hostname: AND-PCBOOK #Implementation: based Synopsys HDL Compiler, version comp201503p1, Build 058R, built Apr 20 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys Verilog Compiler, version comp201503p1, Build 058R, built Apr 20 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @I::"C:\lscc\diamond\3.5\synpbase\lib\lucent\machxo2.v" @I::"C:\lscc\diamond\3.5\synpbase\lib\lucent\pmi_def.v" @I::"C:\lscc\diamond\3.5\synpbase\lib\vlog\hypermods.v" @I::"C:\lscc\diamond\3.5\synpbase\lib\vlog\umr_capim.v" @I::"C:\lscc\diamond\3.5\synpbase\lib\vlog\scemi_objects.v" @I::"C:\lscc\diamond\3.5\synpbase\lib\vlog\scemi_pipes.svh" @I::"D:\SRC\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v" @W:CG1249 : RP2C02_LITE_LAT_V3.v(771) | Redeclaration of implicit signal H_LINE23 @I::"D:\SRC\PPU_LITE_LATTICE_V3\PLL.v" @I::"D:\SRC\PPU_LITE_LATTICE_V3\OAM_RAM.v" @I::"D:\SRC\PPU_LITE_LATTICE_V3\OAM2_RAM.v" @I::"D:\SRC\PPU_LITE_LATTICE_V3\PALETTE_RAM.v" @I::"D:\SRC\PPU_LITE_LATTICE_V3\PALETTE_RGB_TABLE.v" @I::"D:\SRC\PPU_LITE_LATTICE_V3\CODER_NTSC_PAL.v" Verilog syntax check successful! Options changed - recompiling Selecting top level module RP2C02_LITE_LAT_V3 @N:CG364 : machxo2.v(1124) | Synthesizing module VLO @N:CG364 : machxo2.v(1730) | Synthesizing module EHXPLLJ @N:CG364 : PLL.v(8) | Synthesizing module PLL @N:CG364 : RP2C02_LITE_LAT_V3.v(489) | Synthesizing module CLK_DIV @N:CG364 : CODER_NTSC_PAL.v(4) | Synthesizing module CODER_NTSC_PAL @N:CG364 : RP2C02_LITE_LAT_V3.v(521) | Synthesizing module REGISTER_SELECT @N:CG364 : RP2C02_LITE_LAT_V3.v(580) | Synthesizing module REG2000_2001 @N:CG364 : RP2C02_LITE_LAT_V3.v(645) | Synthesizing module READBUSMUX @N:CG364 : RP2C02_LITE_LAT_V3.v(1621) | Synthesizing module COUNTER @N:CG364 : RP2C02_LITE_LAT_V3.v(684) | Synthesizing module TIMING_GENERATOR @N:CG364 : RP2C02_LITE_LAT_V3.v(894) | Synthesizing module LOCAL_BUS_CONTROL @N:CG364 : RP2C02_LITE_LAT_V3.v(1490) | Synthesizing module SHIFTREG @N:CG364 : RP2C02_LITE_LAT_V3.v(951) | Synthesizing module BG_COLOR @N:CG364 : RP2C02_LITE_LAT_V3.v(1036) | Synthesizing module PAR_GEN @N:CG364 : RP2C02_LITE_LAT_V3.v(1187) | Synthesizing module OBJ_EVAL @N:CG364 : RP2C02_LITE_LAT_V3.v(1652) | Synthesizing module OAM_COUNTER @N:CG364 : machxo2.v(1120) | Synthesizing module VHI @N:CG364 : machxo2.v(1291) | Synthesizing module DP8KC @N:CG364 : OAM_RAM.v(8) | Synthesizing module OAM_RAM @N:CG364 : OAM2_RAM.v(8) | Synthesizing module OAM2_RAM @N:CG364 : RP2C02_LITE_LAT_V3.v(1240) | Synthesizing module OAM @N:CG364 : RP2C02_LITE_LAT_V3.v(1457) | Synthesizing module FIFO_HPOSCNT @N:CG364 : RP2C02_LITE_LAT_V3.v(1329) | Synthesizing module OBJ_FIFO @N:CG364 : RP2C02_LITE_LAT_V3.v(1517) | Synthesizing module PIX_MUX @N:CG364 : PALETTE_RAM.v(8) | Synthesizing module PALETTE_RAM @N:CG364 : PALETTE_RGB_TABLE.v(8) | Synthesizing module PALETTE_RGB_TABLE @N:CG364 : RP2C02_LITE_LAT_V3.v(1568) | Synthesizing module PALETTE @N:CG364 : RP2C02_LITE_LAT_V3.v(35) | Synthesizing module RP2C02_LITE_LAT_V3 @W:CL159 : RP2C02_LITE_LAT_V3.v(47) | Input VRAMCS is unused @W:CL159 : RP2C02_LITE_LAT_V3.v(48) | Input VRAMA10 is unused @W:CL159 : RP2C02_LITE_LAT_V3.v(1571) | Input nPCLK is unused At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 80MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Apr 16 21:36:42 2026 ###########################################################] Synopsys Netlist Linker, version comp201503p1, Build 058R, built Apr 20 2015 @N: : | Running in 64-bit mode File D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\based\synwork\layer0.srs changed - recompiling @N:NF107 : RP2C02_LITE_LAT_V3.v(35) | Selected library: work cell: RP2C02_LITE_LAT_V3 view verilog as top level @N:NF107 : RP2C02_LITE_LAT_V3.v(35) | Selected library: work cell: RP2C02_LITE_LAT_V3 view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Apr 16 21:36:43 2026 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Apr 16 21:36:43 2026 ###########################################################] Synopsys Netlist Linker, version comp201503p1, Build 058R, built Apr 20 2015 @N: : | Running in 64-bit mode Options changed - recompiling @N:NF107 : RP2C02_LITE_LAT_V3.v(35) | Selected library: work cell: RP2C02_LITE_LAT_V3 view verilog as top level @N:NF107 : RP2C02_LITE_LAT_V3.v(35) | Selected library: work cell: RP2C02_LITE_LAT_V3 view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Apr 16 21:36:44 2026 ###########################################################] Pre-mapping Report Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1176R, Built Apr 20 2015 17:38:44 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03L Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) Linked File: PPU_LITE_LATTICE_V3_based_scck.rpt Printing clock summary report in "D:\SRC\PPU_LITE_LATTICE_V3\based\PPU_LITE_LATTICE_V3_based_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 105MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 105MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) @W:BN132 : rp2c02_lite_lat_v3.v(815) | Removing sequential instance MOD_TIMING_GENERATOR.VC_LATCH, because it is equivalent to instance MOD_TIMING_GENERATOR.RESCL_IN @N:BN362 : rp2c02_lite_lat_v3.v(507) | Removing sequential instance SUBCLK of view:PrimLib.dff(prim) in hierarchy view:work.CLK_DIV(verilog) because there are no references to its outputs @N:BN362 : rp2c02_lite_lat_v3.v(507) | Removing sequential instance SUB[1:0] of view:PrimLib.dff(prim) in hierarchy view:work.CLK_DIV(verilog) because there are no references to its outputs ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 syn_allowed_resources : blockrams=7 set on top level netlist RP2C02_LITE_LAT_V3 Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ----------------------------------------------------------------------------------------- PLL|CLKOP_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_0 RP2C02_LITE_LAT_V3|MCLK 1.0 MHz 1000.000 inferred Inferred_clkgroup_1 ========================================================================================= @W:MT529 : coder_ntsc_pal.v(108) | Found inferred clock PLL|CLKOP_inferred_clock which controls 1037 sequential elements including MOD_CODER_NTSC_PAL.DIV[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. @W:MT529 : rp2c02_lite_lat_v3.v(507) | Found inferred clock RP2C02_LITE_LAT_V3|MCLK which controls 4 sequential elements including MOD_CLK_DIV.DIV[2:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 145MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Apr 16 21:36:45 2026 ###########################################################] Map & Optimize Report Synopsys Lattice Technology Mapper, Version maplat, Build 1176R, Built Apr 20 2015 17:38:44 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03L Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) @N:BN362 : rp2c02_lite_lat_v3.v(815) | Removing sequential instance RC in hierarchy view:work.TIMING_GENERATOR(verilog) because there are no references to its outputs @W:BN132 : rp2c02_lite_lat_v3.v(1223) | Removing instance MOD_OBJ_EVAL.OBLATCH[7], because it is equivalent to instance MOD_READBUSMUX.OB_R[7] @W:BN132 : rp2c02_lite_lat_v3.v(1223) | Removing instance MOD_OBJ_EVAL.OBLATCH[6], because it is equivalent to instance MOD_READBUSMUX.OB_R[6] @W:BN132 : rp2c02_lite_lat_v3.v(1223) | Removing instance MOD_OBJ_EVAL.OBLATCH[5], because it is equivalent to instance MOD_READBUSMUX.OB_R[5] @W:BN132 : rp2c02_lite_lat_v3.v(1223) | Removing instance MOD_OBJ_EVAL.OBLATCH[4], because it is equivalent to instance MOD_READBUSMUX.OB_R[4] @W:BN132 : rp2c02_lite_lat_v3.v(1223) | Removing instance MOD_OBJ_EVAL.OBLATCH[3], because it is equivalent to instance MOD_READBUSMUX.OB_R[3] @W:BN132 : rp2c02_lite_lat_v3.v(1223) | Removing instance MOD_OBJ_EVAL.OBLATCH[2], because it is equivalent to instance MOD_READBUSMUX.OB_R[2] @W:BN132 : rp2c02_lite_lat_v3.v(1223) | Removing instance MOD_OBJ_EVAL.OBLATCH[1], because it is equivalent to instance MOD_READBUSMUX.OB_R[1] @W:BN132 : rp2c02_lite_lat_v3.v(1223) | Removing instance MOD_OBJ_EVAL.OBLATCH[0], because it is equivalent to instance MOD_READBUSMUX.OB_R[0] @W:BN132 : rp2c02_lite_lat_v3.v(1547) | Removing instance MOD_PIX_MUX.THO_LATCH[1], because it is equivalent to instance MOD_BG_COLOR.THO1R @W:BN132 : rp2c02_lite_lat_v3.v(1607) | Removing instance MOD_PALETTE.DB_PARR, because it is equivalent to instance MOD_LOCAL_BUS_CONTROL.TSTEP_LATCH Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 154MB peak: 155MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 150MB peak: 155MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 155MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 155MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 155MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 155MB) Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 149MB peak: 155MB) Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 172MB peak: 175MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:03s 498.75ns 978 / 1029 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 172MB peak: 175MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. @A:BN291 : rp2c02_lite_lat_v3.v(1547) | Boundary register MOD_PIX_MUX.STEP3_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1547) | Boundary register MOD_PIX_MUX.STEP3_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1547) | Boundary register MOD_PIX_MUX.STEP3_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1547) | Boundary register MOD_PIX_MUX.STEP3_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1607) | Boundary register MOD_PALETTE.PIX_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1607) | Boundary register MOD_PALETTE.PIX_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1607) | Boundary register MOD_PALETTE.PIX_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1607) | Boundary register MOD_PALETTE.PIX_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1412) | Boundary register MOD_OBJ_FIFO.SEL_LATCH_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1412) | Boundary register MOD_OBJ_FIFO.SEL_LATCH_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1412) | Boundary register MOD_OBJ_FIFO.SEL_LATCH_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1412) | Boundary register MOD_OBJ_FIFO.SEL_LATCH_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1300) | Boundary register MOD_OAM.OB_7_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1300) | Boundary register MOD_OAM.OB_6_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1300) | Boundary register MOD_OAM.OB_5_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1300) | Boundary register MOD_OAM.OB_4_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1300) | Boundary register MOD_OAM.OB_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1300) | Boundary register MOD_OAM.OB_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1300) | Boundary register MOD_OAM.OB_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1300) | Boundary register MOD_OAM.OB_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1671) | Boundary register MOD_OAM.OAMCNT.CNT_6_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1671) | Boundary register MOD_OAM.OAMCNT.CNT_5_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1671) | Boundary register MOD_OAM.OAMCNT.CNT_4_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1671) | Boundary register MOD_OAM.OAMCNT.CNT_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1671) | Boundary register MOD_OAM.OAMCNT.CNT_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A:BN291 : rp2c02_lite_lat_v3.v(1671) | Boundary register MOD_OAM.OAMCNT.CNT_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 174MB peak: 175MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 4 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 1030 clock pin(s) of sequential element(s) 0 instances converted, 1030 sequential instances remain driven by gated/generated clocks ============================= Non-Gated/Non-Generated Clocks ============================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------ ClockId0002 MCLK port 4 MOD_CLK_DIV.DIV[2] ========================================================================================== ==================================================================================================== Gated/Generated Clocks ===================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 MOD_PLL.PLLInst_0 EHXPLLJ 1030 MOD_READBUSMUX.Do[7] Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements ================================================================================================================================================================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 136MB peak: 175MB) Writing Analyst data base D:\SRC\PPU_LITE_LATTICE_V3\based\synwork\PPU_LITE_LATTICE_V3_based_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 173MB peak: 176MB) Writing EDIF Netlist and constraint files J-2015.03L @N:BW106 : | Synplicity Constraint File capacitance units using default value of 1pF Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 178MB peak: 180MB) Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 176MB peak: 180MB) @W:MT246 : pll.v(64) | Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock RP2C02_LITE_LAT_V3|MCLK with period 1000.00ns. Please declare a user-defined clock on object "p:MCLK" @W:MT420 : | Found inferred clock PLL|CLKOP_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:MOD_PLL.CLKOP" @S |##### START OF TIMING REPORT #####[ # Timing Report written on Thu Apr 16 21:36:50 2026 # Top view: RP2C02_LITE_LAT_V3 Requested Frequency: 1.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 498.715 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------------------- PLL|CLKOP_inferred_clock 1.0 MHz 82.9 MHz 1000.000 12.058 987.942 inferred Inferred_clkgroup_0 RP2C02_LITE_LAT_V3|MCLK 1.0 MHz 389.0 MHz 1000.000 2.571 498.715 inferred Inferred_clkgroup_1 ================================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------- PLL|CLKOP_inferred_clock PLL|CLKOP_inferred_clock | 1000.000 987.942 | No paths - | No paths - | No paths - RP2C02_LITE_LAT_V3|MCLK PLL|CLKOP_inferred_clock | Diff grp - | No paths - | No paths - | Diff grp - RP2C02_LITE_LAT_V3|MCLK RP2C02_LITE_LAT_V3|MCLK | 1000.000 998.292 | No paths - | 500.000 498.715 | No paths - ============================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: PLL|CLKOP_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------- MOD_TIMING_GENERATOR.VCNT\[0\].CNT PLL|CLKOP_inferred_clock FD1P3AX Q Vo[0] 1.256 987.942 MOD_READBUSMUX.OB_R[0] PLL|CLKOP_inferred_clock FD1P3AX Q OB_R[0] 1.108 988.090 MOD_TIMING_GENERATOR.VCNT\[1\].CNT PLL|CLKOP_inferred_clock FD1P3AX Q Vo[1] 1.244 988.097 MOD_TIMING_GENERATOR.VCNT\[2\].CNT PLL|CLKOP_inferred_clock FD1P3AX Q Vo[2] 1.228 988.113 MOD_TIMING_GENERATOR.VCNT\[3\].CNT PLL|CLKOP_inferred_clock FD1P3AX Q Vo[3] 1.244 988.240 MOD_TIMING_GENERATOR.VCNT\[4\].CNT PLL|CLKOP_inferred_clock FD1P3AX Q Vo[4] 1.228 988.255 MOD_READBUSMUX.OB_R[1] PLL|CLKOP_inferred_clock FD1P3AX Q OB_R[1] 1.044 988.297 MOD_READBUSMUX.OB_R[2] PLL|CLKOP_inferred_clock FD1P3AX Q OB_R[2] 1.044 988.297 MOD_READBUSMUX.OB_R[3] PLL|CLKOP_inferred_clock FD1P3AX Q OB_R[3] 1.044 988.439 MOD_READBUSMUX.OB_R[4] PLL|CLKOP_inferred_clock FD1P3AX Q OB_R[4] 1.044 988.439 ======================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------- MOD_OAM.OAMCNT.CNT1[5] PLL|CLKOP_inferred_clock FD1P3AX D N_34_i_0 999.894 987.942 MOD_OAM.OAMCNT.CNT1[6] PLL|CLKOP_inferred_clock FD1P3AX D N_33_i_0 999.894 987.942 MOD_OAM.OAMCNT.CNT1[7] PLL|CLKOP_inferred_clock FD1P3AX D N_32_i_0 999.894 987.942 MOD_OAM.OAMCNT.CNT1[2] PLL|CLKOP_inferred_clock FD1P3AX D N_37_i 999.894 989.095 MOD_OAM.OAMCNT.CNT1[3] PLL|CLKOP_inferred_clock FD1P3AX D N_36_i_0 999.894 989.095 MOD_OAM.OAMCNT.CNT1[4] PLL|CLKOP_inferred_clock FD1P3AX D N_35_i_0 999.894 989.095 MOD_OAM.OMV_LATCH PLL|CLKOP_inferred_clock FD1P3AX D OMV_LATCH_2 999.894 989.271 MOD_OAM.OAMCNT.CNT1[1] PLL|CLKOP_inferred_clock FD1P3AX D CNT1_2[1] 999.894 990.288 MOD_OAM.OMFG_LATCH PLL|CLKOP_inferred_clock FD1P3AX D N_45_mux 999.894 990.736 MOD_OAM.OAMCNT.CNT1[0] PLL|CLKOP_inferred_clock FD1P3AX D CNT1_2[0] 999.894 991.480 ================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 999.894 - Propagation time: 11.953 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 987.942 Number of logic level(s): 11 Starting point: MOD_TIMING_GENERATOR.VCNT\[0\].CNT / Q Ending point: MOD_OAM.OAMCNT.CNT1[5] / D The start point is clocked by PLL|CLKOP_inferred_clock [rising] on pin CK The end point is clocked by PLL|CLKOP_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------- MOD_TIMING_GENERATOR.VCNT\[0\].CNT FD1P3AX Q Out 1.256 1.256 - Vo[0] Net - - - - 14 MOD_OBJ_EVAL.OVS_cry_0_0 CCU2D A1 In 0.000 1.256 - MOD_OBJ_EVAL.OVS_cry_0_0 CCU2D COUT Out 1.545 2.800 - OVS_cry_0 Net - - - - 1 MOD_OBJ_EVAL.OVS_cry_1_0 CCU2D CIN In 0.000 2.800 - MOD_OBJ_EVAL.OVS_cry_1_0 CCU2D COUT Out 0.143 2.943 - OVS_cry_2 Net - - - - 1 MOD_OBJ_EVAL.OVS_cry_3_0 CCU2D CIN In 0.000 2.943 - MOD_OBJ_EVAL.OVS_cry_3_0 CCU2D COUT Out 0.143 3.086 - OVS_cry_4 Net - - - - 1 MOD_OBJ_EVAL.OVS_cry_5_0 CCU2D CIN In 0.000 3.086 - MOD_OBJ_EVAL.OVS_cry_5_0 CCU2D S1 Out 1.549 4.635 - OVS[6] Net - - - - 1 MOD_OBJ_EVAL.OVS_cry_5_0_RNIVTBD1 ORCALUT4 B In 0.000 4.635 - MOD_OBJ_EVAL.OVS_cry_5_0_RNIVTBD1 ORCALUT4 Z Out 1.089 5.724 - m4_4 Net - - - - 2 MOD_OBJ_EVAL.OVS_s_7_0_RNI3QK84 ORCALUT4 D In 0.000 5.724 - MOD_OBJ_EVAL.OVS_s_7_0_RNI3QK84 ORCALUT4 Z Out 1.017 6.740 - N_41_mux Net - - - - 1 MOD_OBJ_EVAL.OVS_s_7_0_RNIJL455 ORCALUT4 B In 0.000 6.740 - MOD_OBJ_EVAL.OVS_s_7_0_RNIJL455 ORCALUT4 Z Out 1.225 7.965 - un1_DO_COPY_i_0 Net - - - - 5 MOD_OBJ_EVAL.CLATCH_RNIEGQJ6[5] ORCALUT4 A In 0.000 7.965 - MOD_OBJ_EVAL.CLATCH_RNIEGQJ6[5] ORCALUT4 Z Out 1.193 9.158 - N_45_mux Net - - - - 4 MOD_OBJ_EVAL.CLATCH_RNIP83L7_0[5] ORCALUT4 C In 0.000 9.158 - MOD_OBJ_EVAL.CLATCH_RNIP83L7_0[5] ORCALUT4 Z Out 1.193 10.351 - N_26 Net - - - - 4 MOD_OBJ_EVAL.CLATCH_RNINAK09_0[5] ORCALUT4 D In 0.000 10.351 - MOD_OBJ_EVAL.CLATCH_RNINAK09_0[5] ORCALUT4 Z Out 1.153 11.504 - N_29 Net - - - - 3 MOD_OBJ_EVAL.CLATCH_RNI3O4F9[5] ORCALUT4 B In 0.000 11.504 - MOD_OBJ_EVAL.CLATCH_RNI3O4F9[5] ORCALUT4 Z Out 0.449 11.953 - N_34_i_0 Net - - - - 1 MOD_OAM.OAMCNT.CNT1[5] FD1P3AX D In 0.000 11.953 - ===================================================================================================== ==================================== Detailed Report for Clock: RP2C02_LITE_LAT_V3|MCLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------- MOD_CLK_DIV.DIV[1] RP2C02_LITE_LAT_V3|MCLK FD1S3AX Q DIV[1] 1.180 498.715 MOD_CLK_DIV.DIV[2] RP2C02_LITE_LAT_V3|MCLK FD1S3AX Q DIV[2] 1.108 998.364 MOD_CLK_DIV.DIV[0] RP2C02_LITE_LAT_V3|MCLK FD1S3AX Q DIV[0] 0.972 998.923 ===================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------- MOD_CLK_DIV.DIV2n RP2C02_LITE_LAT_V3|MCLK FD1S3IX D DIV[1] 499.894 498.715 MOD_CLK_DIV.DIV[0] RP2C02_LITE_LAT_V3|MCLK FD1S3AX D un2_DIV_i 1000.089 998.292 MOD_CLK_DIV.DIV[2] RP2C02_LITE_LAT_V3|MCLK FD1S3AX D DIV2n_2 1000.089 998.292 MOD_CLK_DIV.DIV[1] RP2C02_LITE_LAT_V3|MCLK FD1S3AX D DIV[0] 999.894 998.923 ========================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 500.000 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 499.894 - Propagation time: 1.180 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 498.715 Number of logic level(s): 0 Starting point: MOD_CLK_DIV.DIV[1] / Q Ending point: MOD_CLK_DIV.DIV2n / D The start point is clocked by RP2C02_LITE_LAT_V3|MCLK [rising] on pin CK The end point is clocked by RP2C02_LITE_LAT_V3|MCLK [falling] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------ MOD_CLK_DIV.DIV[1] FD1S3AX Q Out 1.180 1.180 - DIV[1] Net - - - - 5 MOD_CLK_DIV.DIV2n FD1S3IX D In 0.000 1.180 - ==================================================================================== ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 177MB peak: 180MB) Finished timing report (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 177MB peak: 180MB) --------------------------------------- Resource Usage Report Part: lcmxo2_1200hc-4 Register bits: 1029 of 1280 (80%) PIC Latch: 0 I/O cells: 69 Block Rams : 4 of 7 (57%) Details: BB: 16 CCU2D: 5 DP8KC: 4 EHXPLLJ: 1 FD1P3AX: 903 FD1P3DX: 10 FD1P3IX: 18 FD1P3JX: 10 FD1S3AX: 37 FD1S3IX: 30 GSR: 1 IB: 11 IFS1P3DX: 21 INV: 35 L6MUX21: 5 OB: 39 OBZ: 3 ORCALUT4: 947 PFUMX: 17 PUR: 1 VHI: 152 VLO: 136 false: 17 true: 1 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 58MB peak: 180MB) Process took 0h:00m:05s realtime, 0h:00m:05s cputime # Thu Apr 16 21:36:51 2026 ###########################################################]