Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1176R, Built Apr 20 2015 17:38:44
Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
Product Version J-2015.03L

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@L: D:\RadioSoft\VIDEO GAME\DENDY\SRC\PPU_LITE_LATTICE_V3\based\PPU_LITE_LATTICE_V3_based_scck.rpt 
Printing clock  summary report in "D:\RadioSoft\VIDEO GAME\DENDY\SRC\PPU_LITE_LATTICE_V3\based\PPU_LITE_LATTICE_V3_based_scck.rpt" file 
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 105MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 105MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)

@W:BN132 : rp2c02_lite_lat_v3.v(820) | Removing sequential instance MOD_TIMING_GENERATOR.VC_LATCH,  because it is equivalent to instance MOD_TIMING_GENERATOR.RESCL_IN
@N:BN362 : rp2c02_lite_lat_v3.v(508) | Removing sequential instance SUBCLK of view:PrimLib.dff(prim) in hierarchy view:work.CLK_DIV(verilog) because there are no references to its outputs 
@N:BN362 : rp2c02_lite_lat_v3.v(508) | Removing sequential instance SUB[1:0] of view:PrimLib.dff(prim) in hierarchy view:work.CLK_DIV(verilog) because there are no references to its outputs 
ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=7  set on top level netlist RP2C02_LITE_LAT

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)



@S |Clock Summary
*****************

Start                        Requested     Requested     Clock        Clock              
Clock                        Frequency     Period        Type         Group              
-----------------------------------------------------------------------------------------
PLL|CLKOP_inferred_clock     1.0 MHz       1000.000      inferred     Inferred_clkgroup_0
RP2C02_LITE_LAT|MCLK         1.0 MHz       1000.000      inferred     Inferred_clkgroup_1
=========================================================================================

@W:MT529 : coder_ntsc_pal.v(107) | Found inferred clock PLL|CLKOP_inferred_clock which controls 1037 sequential elements including MOD_CODER_NTSC_PAL.DIV[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W:MT529 : rp2c02_lite_lat_v3.v(508) | Found inferred clock RP2C02_LITE_LAT|MCLK which controls 6 sequential elements including MOD_CLK_DIV.PCLK_P[2:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 80MB peak: 143MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Mar 14 18:08:48 2026

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