• proj_1 (based)
  • Synthesis -
    • Mapper Report
      • Clock Conversion
      • Timing Report
        • Performance Summary
        • Clock Relationships
        • Interface Information
        • Detailed Report for Clocks
          • Clock: PLL|CLKOP_inferred_clock
            • Starting Points with Worst Slack
            • Ending Points with Worst Slack
            • Worst Path Information
          • Clock: RP2C02_LITE_LAT|MCLK
            • Starting Points with Worst Slack
            • Ending Points with Worst Slack
            • Worst Path Information
      • Resource Utilization
  • Place and Route -
    • Xilinx Timing Report (18:09 14-Mar)
  • Session Log (18:11 14-Mar)