Synopsys Lattice Technology Mapper, Version maplat, Build 1176R, Built Apr 20 2015 17:38:44
Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
Product Version J-2015.03L
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
@N:MF248 : | Running in 64-bit mode.
@N:MF666 : | Clock conversion enabled
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB)
Available hyper_sources - for debug and ip models
None Found
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
@N:BN362 : rp2c02_lite_lat_v3.v(820) | Removing sequential instance RC in hierarchy view:work.TIMING_GENERATOR(verilog) because there are no references to its outputs
@W:BN132 : rp2c02_lite_lat_v3.v(1252) | Removing instance MOD_OBJ_EVAL.OBLATCH[7], because it is equivalent to instance MOD_READBUSMUX.OB_R[7]
@W:BN132 : rp2c02_lite_lat_v3.v(1252) | Removing instance MOD_OBJ_EVAL.OBLATCH[6], because it is equivalent to instance MOD_READBUSMUX.OB_R[6]
@W:BN132 : rp2c02_lite_lat_v3.v(1252) | Removing instance MOD_OBJ_EVAL.OBLATCH[5], because it is equivalent to instance MOD_READBUSMUX.OB_R[5]
@W:BN132 : rp2c02_lite_lat_v3.v(1252) | Removing instance MOD_OBJ_EVAL.OBLATCH[4], because it is equivalent to instance MOD_READBUSMUX.OB_R[4]
@W:BN132 : rp2c02_lite_lat_v3.v(1252) | Removing instance MOD_OBJ_EVAL.OBLATCH[3], because it is equivalent to instance MOD_READBUSMUX.OB_R[3]
@W:BN132 : rp2c02_lite_lat_v3.v(1252) | Removing instance MOD_OBJ_EVAL.OBLATCH[2], because it is equivalent to instance MOD_READBUSMUX.OB_R[2]
@W:BN132 : rp2c02_lite_lat_v3.v(1252) | Removing instance MOD_OBJ_EVAL.OBLATCH[1], because it is equivalent to instance MOD_READBUSMUX.OB_R[1]
@W:BN132 : rp2c02_lite_lat_v3.v(1252) | Removing instance MOD_OBJ_EVAL.OBLATCH[0], because it is equivalent to instance MOD_READBUSMUX.OB_R[0]
@W:BN132 : rp2c02_lite_lat_v3.v(1589) | Removing instance MOD_PIX_MUX.THO_LATCH[1], because it is equivalent to instance MOD_BG_COLOR.THO1R
@W:BN132 : rp2c02_lite_lat_v3.v(1649) | Removing instance MOD_PALETTE.DB_PARR, because it is equivalent to instance MOD_LOCAL_BUS_CONTROL.TSTEP_LATCH
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 153MB peak: 153MB)
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 148MB peak: 153MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 148MB peak: 153MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 153MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 153MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 153MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 153MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 163MB peak: 165MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s 498.79ns 954 / 1031
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 163MB peak: 165MB)
@N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@A:BN291 : rp2c02_lite_lat_v3.v(1680) | Boundary register MOD_PAR_GEN.TVCNT\[4\].CNT.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1680) | Boundary register MOD_PAR_GEN.TVCNT\[3\].CNT.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1680) | Boundary register MOD_PAR_GEN.TVCNT\[2\].CNT.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1680) | Boundary register MOD_PAR_GEN.TVCNT\[1\].CNT.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1680) | Boundary register MOD_PAR_GEN.TVCNT\[0\].CNT.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1589) | Boundary register MOD_PIX_MUX.STEP3_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1589) | Boundary register MOD_PIX_MUX.STEP3_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1589) | Boundary register MOD_PIX_MUX.STEP3_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1589) | Boundary register MOD_PIX_MUX.STEP3_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1649) | Boundary register MOD_PALETTE.PIX_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1649) | Boundary register MOD_PALETTE.PIX_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1649) | Boundary register MOD_PALETTE.PIX_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1649) | Boundary register MOD_PALETTE.PIX_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1452) | Boundary register MOD_OBJ_FIFO.SEL_LATCH_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1452) | Boundary register MOD_OBJ_FIFO.SEL_LATCH_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1452) | Boundary register MOD_OBJ_FIFO.SEL_LATCH_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1452) | Boundary register MOD_OBJ_FIFO.SEL_LATCH_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1519) | Boundary register MOD_OBJ_FIFO.HPOSCNT7.EN.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1519) | Boundary register MOD_OBJ_FIFO.HPOSCNT6.EN.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1519) | Boundary register MOD_OBJ_FIFO.HPOSCNT5.EN.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1519) | Boundary register MOD_OBJ_FIFO.HPOSCNT4.EN.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1519) | Boundary register MOD_OBJ_FIFO.HPOSCNT3.EN.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1519) | Boundary register MOD_OBJ_FIFO.HPOSCNT2.EN.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1519) | Boundary register MOD_OBJ_FIFO.HPOSCNT1.EN.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1519) | Boundary register MOD_OBJ_FIFO.HPOSCNT0.EN.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1341) | Boundary register MOD_OAM.OB_7_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1341) | Boundary register MOD_OAM.OB_6_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1341) | Boundary register MOD_OAM.OB_5_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1341) | Boundary register MOD_OAM.OB_4_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1341) | Boundary register MOD_OAM.OB_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1341) | Boundary register MOD_OAM.OB_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1341) | Boundary register MOD_OAM.OB_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1341) | Boundary register MOD_OAM.OB_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1711) | Boundary register MOD_OAM.OAMCNT.CNT_7_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1711) | Boundary register MOD_OAM.OAMCNT.CNT_6_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1711) | Boundary register MOD_OAM.OAMCNT.CNT_5_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1711) | Boundary register MOD_OAM.OAMCNT.CNT_4_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1711) | Boundary register MOD_OAM.OAMCNT.CNT_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1711) | Boundary register MOD_OAM.OAMCNT.CNT_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1711) | Boundary register MOD_OAM.OAMCNT.CNT_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(1711) | Boundary register MOD_OAM.OAMCNT.CNT_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(820) | Boundary register MOD_TIMING_GENERATOR.H_8_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(820) | Boundary register MOD_TIMING_GENERATOR.H_7_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(820) | Boundary register MOD_TIMING_GENERATOR.H_6_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(820) | Boundary register MOD_TIMING_GENERATOR.H_5_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(820) | Boundary register MOD_TIMING_GENERATOR.H_4_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(820) | Boundary register MOD_TIMING_GENERATOR.H_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(820) | Boundary register MOD_TIMING_GENERATOR.H_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(820) | Boundary register MOD_TIMING_GENERATOR.H_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(820) | Boundary register MOD_TIMING_GENERATOR.H_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(820) | Boundary register MOD_TIMING_GENERATOR.V_8_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(820) | Boundary register MOD_TIMING_GENERATOR.V_7_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(820) | Boundary register MOD_TIMING_GENERATOR.V_6_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(820) | Boundary register MOD_TIMING_GENERATOR.V_5_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(820) | Boundary register MOD_TIMING_GENERATOR.V_4_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(820) | Boundary register MOD_TIMING_GENERATOR.V_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(820) | Boundary register MOD_TIMING_GENERATOR.V_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(820) | Boundary register MOD_TIMING_GENERATOR.V_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
@A:BN291 : rp2c02_lite_lat_v3.v(820) | Boundary register MOD_TIMING_GENERATOR.V_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 163MB peak: 165MB)
#### START OF CLOCK OPTIMIZATION REPORT #####[
1 non-gated/non-generated clock tree(s) driving 6 clock pin(s) of sequential element(s)
1 gated/generated clock tree(s) driving 1030 clock pin(s) of sequential element(s)
0 instances converted, 1030 sequential instances remain driven by gated/generated clocks
============================== Non-Gated/Non-Generated Clocks ===============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------------
ClockId0002 MCLK port 6 MOD_CLK_DIV.PCLK_N[1]
=============================================================================================
====================================================================================================== Gated/Generated Clocks ======================================================================================================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0001 MOD_PLL.PLLInst_0 EHXPLLJ 1030 MOD_REG2000_2001.BGCLIP Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements
====================================================================================================================================================================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######]
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 126MB peak: 165MB)
Writing Analyst data base D:\RadioSoft\VIDEO GAME\DENDY\SRC\PPU_LITE_LATTICE_V3\based\synwork\PPU_LITE_LATTICE_V3_based_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 162MB peak: 165MB)
Writing EDIF Netlist and constraint files
J-2015.03L
@N:BW106 : | Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 166MB peak: 168MB)
Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 165MB peak: 168MB)
@W:MT246 : pll.v(64) | Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT420 : | Found inferred clock RP2C02_LITE_LAT|MCLK with period 1000.00ns. Please declare a user-defined clock on object "p:MCLK"
@W:MT420 : | Found inferred clock PLL|CLKOP_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:MOD_PLL.CLKOP"
@S |##### START OF TIMING REPORT #####[
# Timing Report written on Sat Mar 14 18:08:51 2026
#
Top view: RP2C02_LITE_LAT
Requested Frequency: 1.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.
Performance Summary
*******************
Worst slack in design: 498.787
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
---------------------------------------------------------------------------------------------------------------------------------
PLL|CLKOP_inferred_clock 1.0 MHz 105.7 MHz 1000.000 9.465 990.535 inferred Inferred_clkgroup_0
RP2C02_LITE_LAT|MCLK 1.0 MHz 412.1 MHz 1000.000 2.427 498.787 inferred Inferred_clkgroup_1
=================================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------------------------------------
PLL|CLKOP_inferred_clock PLL|CLKOP_inferred_clock | 1000.000 990.535 | No paths - | No paths - | No paths -
RP2C02_LITE_LAT|MCLK PLL|CLKOP_inferred_clock | Diff grp - | No paths - | No paths - | Diff grp -
RP2C02_LITE_LAT|MCLK RP2C02_LITE_LAT|MCLK | 1000.000 998.204 | No paths - | 500.000 498.787 | No paths -
==============================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: PLL|CLKOP_inferred_clock
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------
MOD_TIMING_GENERATOR.V[0] PLL|CLKOP_inferred_clock FD1P3IX Q Vo[0] 1.256 990.535
MOD_READBUSMUX.OB_R[0] PLL|CLKOP_inferred_clock FD1P3AX Q OB_R[0] 1.108 990.683
MOD_TIMING_GENERATOR.V[1] PLL|CLKOP_inferred_clock FD1P3IX Q Vo[1] 1.244 990.690
MOD_TIMING_GENERATOR.V[2] PLL|CLKOP_inferred_clock FD1P3IX Q Vo[2] 1.232 990.702
MOD_TIMING_GENERATOR.V[3] PLL|CLKOP_inferred_clock FD1P3IX Q Vo[3] 1.252 990.825
MOD_TIMING_GENERATOR.V[4] PLL|CLKOP_inferred_clock FD1P3IX Q Vo[4] 1.252 990.825
MOD_READBUSMUX.OB_R[1] PLL|CLKOP_inferred_clock FD1P3AX Q OB_R[1] 1.044 990.890
MOD_READBUSMUX.OB_R[2] PLL|CLKOP_inferred_clock FD1P3AX Q OB_R[2] 1.044 990.890
MOD_READBUSMUX.OB_R[3] PLL|CLKOP_inferred_clock FD1P3AX Q OB_R[3] 1.044 991.033
MOD_READBUSMUX.OB_R[4] PLL|CLKOP_inferred_clock FD1P3AX Q OB_R[4] 1.044 991.033
==============================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------------------------------------
MOD_OAM.OMV_LATCH PLL|CLKOP_inferred_clock FD1P3AX D OMV 999.894 990.535
MOD_OAM.OAMCNT.CNT1[1] PLL|CLKOP_inferred_clock FD1P3AX D CNT1_2[1] 1000.089 991.026
MOD_OAM.OAMCNT.CNT1[2] PLL|CLKOP_inferred_clock FD1P3AX D CNT1_2[2] 1000.089 991.026
MOD_OAM.OAMCNT.CNT1[3] PLL|CLKOP_inferred_clock FD1P3AX D CNT1_2[3] 1000.089 991.026
MOD_OAM.OAMCNT.CNT1[4] PLL|CLKOP_inferred_clock FD1P3AX D CNT1_2[4] 1000.089 991.026
MOD_OAM.OAMCNT.CNT1[5] PLL|CLKOP_inferred_clock FD1P3AX D CNT1_2[5] 1000.462 991.103
MOD_OAM.OAMCNT.CNT1[6] PLL|CLKOP_inferred_clock FD1P3AX D CNT1_2[6] 1000.462 991.103
MOD_OAM.OAMCNT.CNT1[7] PLL|CLKOP_inferred_clock FD1P3AX D CNT1_2[7] 1000.462 991.103
MOD_OAM.OMFG_LATCH PLL|CLKOP_inferred_clock FD1P3AX D un1_OMFG_i 999.894 991.448
MOD_OAM.OSTEP[2] PLL|CLKOP_inferred_clock FD1P3AX D CLATCH_RNIA3IU1[5] 999.894 991.448
=======================================================================================================================
Worst Path Information
View Worst Path in Analyst
***********************
Path information for path number 1:
Requested Period: 1000.000
- Setup time: 0.106
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 999.894
- Propagation time: 9.359
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : 990.535
Number of logic level(s): 9
Starting point: MOD_TIMING_GENERATOR.V[0] / Q
Ending point: MOD_OAM.OMV_LATCH / D
The start point is clocked by PLL|CLKOP_inferred_clock [rising] on pin CK
The end point is clocked by PLL|CLKOP_inferred_clock [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------
MOD_TIMING_GENERATOR.V[0] FD1P3IX Q Out 1.256 1.256 -
Vo[0] Net - - - - 14
MOD_OBJ_EVAL.OVS_cry_0_0 CCU2D A1 In 0.000 1.256 -
MOD_OBJ_EVAL.OVS_cry_0_0 CCU2D COUT Out 1.545 2.800 -
OVS_cry_0 Net - - - - 1
MOD_OBJ_EVAL.OVS_cry_1_0 CCU2D CIN In 0.000 2.800 -
MOD_OBJ_EVAL.OVS_cry_1_0 CCU2D COUT Out 0.143 2.943 -
OVS_cry_2 Net - - - - 1
MOD_OBJ_EVAL.OVS_cry_3_0 CCU2D CIN In 0.000 2.943 -
MOD_OBJ_EVAL.OVS_cry_3_0 CCU2D COUT Out 0.143 3.086 -
OVS_cry_4 Net - - - - 1
MOD_OBJ_EVAL.OVS_cry_5_0 CCU2D CIN In 0.000 3.086 -
MOD_OBJ_EVAL.OVS_cry_5_0 CCU2D S1 Out 1.549 4.635 -
OVS[6] Net - - - - 1
MOD_OBJ_EVAL.OVZ_4 ORCALUT4 B In 0.000 4.635 -
MOD_OBJ_EVAL.OVZ_4 ORCALUT4 Z Out 1.017 5.652 -
OVZ_4 Net - - - - 1
MOD_OBJ_EVAL.OVZ ORCALUT4 D In 0.000 5.652 -
MOD_OBJ_EVAL.OVZ ORCALUT4 Z Out 1.153 6.805 -
OVZ Net - - - - 3
MOD_OBJ_EVAL.un1_DO_COPY ORCALUT4 B In 0.000 6.805 -
MOD_OBJ_EVAL.un1_DO_COPY ORCALUT4 Z Out 1.193 7.997 -
un1_DO_COPY Net - - - - 4
MOD_OAM.un1_MODE4 ORCALUT4 C In 0.000 7.997 -
MOD_OAM.un1_MODE4 ORCALUT4 Z Out 0.449 8.446 -
un1_MODE4 Net - - - - 8
MOD_OAM.OAMCNT.C_OUT PFUMX C0 In 0.000 8.446 -
MOD_OAM.OAMCNT.C_OUT PFUMX Z Out 0.913 9.359 -
OMV Net - - - - 1
MOD_OAM.OMV_LATCH FD1P3AX D In 0.000 9.359 -
============================================================================================
====================================
Detailed Report for Clock: RP2C02_LITE_LAT|MCLK
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------
MOD_CLK_DIV.PCLK_P[1] RP2C02_LITE_LAT|MCLK FD1S3AX Q PCLK_P[1] 1.108 498.787
MOD_CLK_DIV.PCLK_N[1] RP2C02_LITE_LAT|MCLK FD1S3AX Q PCLK_N[1] 1.268 998.204
MOD_CLK_DIV.PCLK_P[2] RP2C02_LITE_LAT|MCLK FD1S3AX Q PCLK_P[2] 1.268 998.204
MOD_CLK_DIV.PCLK_N[0] RP2C02_LITE_LAT|MCLK FD1S3AX Q PCLK_N[0] 0.972 998.923
MOD_CLK_DIV.PCLK_P[0] RP2C02_LITE_LAT|MCLK FD1S3AX Q PCLK_P[0] 0.972 998.923
========================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------
MOD_CLK_DIV.PCLK_P[3] RP2C02_LITE_LAT|MCLK FD1S3AX D PCLK_P[1] 499.894 498.787
MOD_CLK_DIV.PCLK_N[0] RP2C02_LITE_LAT|MCLK FD1S3AX D un2_PCLK_N_i 1000.089 998.204
MOD_CLK_DIV.PCLK_P[0] RP2C02_LITE_LAT|MCLK FD1S3AX D un2_PCLK_P_i 1000.089 998.204
MOD_CLK_DIV.PCLK_P[2] RP2C02_LITE_LAT|MCLK FD1S3AX D PCLK_P[1] 999.894 998.787
MOD_CLK_DIV.PCLK_N[1] RP2C02_LITE_LAT|MCLK FD1S3AX D PCLK_N[0] 999.894 998.923
MOD_CLK_DIV.PCLK_P[1] RP2C02_LITE_LAT|MCLK FD1S3AX D PCLK_P[0] 999.894 998.923
============================================================================================================
Worst Path Information
View Worst Path in Analyst
***********************
Path information for path number 1:
Requested Period: 500.000
- Setup time: 0.106
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 499.894
- Propagation time: 1.108
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 498.787
Number of logic level(s): 0
Starting point: MOD_CLK_DIV.PCLK_P[1] / Q
Ending point: MOD_CLK_DIV.PCLK_P[3] / D
The start point is clocked by RP2C02_LITE_LAT|MCLK [rising] on pin CK
The end point is clocked by RP2C02_LITE_LAT|MCLK [falling] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------
MOD_CLK_DIV.PCLK_P[1] FD1S3AX Q Out 1.108 1.108 -
PCLK_P[1] Net - - - - 3
MOD_CLK_DIV.PCLK_P[3] FD1S3AX D In 0.000 1.108 -
=======================================================================================
##### END OF TIMING REPORT #####]
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 165MB peak: 168MB)
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 165MB peak: 168MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_1200hc-4
Register bits: 1031 of 1280 (81%)
PIC Latch: 0
I/O cells: 69
Block Rams : 4 of 7 (57%)
Details:
BB: 16
CCU2D: 5
DP8KC: 4
EHXPLLJ: 1
FD1P3AX: 885
FD1P3IX: 51
FD1P3JX: 10
FD1S3AX: 35
FD1S3IX: 29
GSR: 1
IB: 11
IFS1P3DX: 21
INV: 43
L6MUX21: 5
OB: 39
OBZ: 3
ORCALUT4: 922
PFUMX: 19
PUR: 1
VHI: 66
VLO: 65
false: 2
true: 1
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 57MB peak: 168MB)
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Sat Mar 14 18:08:51 2026
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