@W: BN132 :"d:\ppu_reverse\fpga\ppu_lite_lattice_v3\rp2c02_lite_lat_v3.v":814:0:814:5|Removing sequential instance MOD_TIMING_GENERATOR.VC_LATCH,  because it is equivalent to instance MOD_TIMING_GENERATOR.RESCL_IN
@W: MT529 :"d:\ppu_reverse\fpga\ppu_lite_lattice_v3\coder_ntsc_pal.v":108:0:108:5|Found inferred clock PLL|CLKOP_inferred_clock which controls 1037 sequential elements including MOD_CODER_NTSC_PAL.DIV[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"d:\ppu_reverse\fpga\ppu_lite_lattice_v3\rp2c02_lite_lat_v3.v":506:0:506:5|Found inferred clock RP2C02_LITE_LAT_V3|MCLK which controls 6 sequential elements including MOD_CLK_DIV.PCLK_P[2:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
