@W: BN132 :"d:\ppu_reverse\fpga\ppu_lite_lattice_v3\rp2c02_lite_lat_v3.v":1233:0:1233:5|Removing instance MOD_OBJ_EVAL.OBLATCH[7],  because it is equivalent to instance MOD_READBUSMUX.OB_R[7]
@W: BN132 :"d:\ppu_reverse\fpga\ppu_lite_lattice_v3\rp2c02_lite_lat_v3.v":1233:0:1233:5|Removing instance MOD_OBJ_EVAL.OBLATCH[6],  because it is equivalent to instance MOD_READBUSMUX.OB_R[6]
@W: BN132 :"d:\ppu_reverse\fpga\ppu_lite_lattice_v3\rp2c02_lite_lat_v3.v":1233:0:1233:5|Removing instance MOD_OBJ_EVAL.OBLATCH[5],  because it is equivalent to instance MOD_READBUSMUX.OB_R[5]
@W: BN132 :"d:\ppu_reverse\fpga\ppu_lite_lattice_v3\rp2c02_lite_lat_v3.v":1233:0:1233:5|Removing instance MOD_OBJ_EVAL.OBLATCH[4],  because it is equivalent to instance MOD_READBUSMUX.OB_R[4]
@W: BN132 :"d:\ppu_reverse\fpga\ppu_lite_lattice_v3\rp2c02_lite_lat_v3.v":1233:0:1233:5|Removing instance MOD_OBJ_EVAL.OBLATCH[3],  because it is equivalent to instance MOD_READBUSMUX.OB_R[3]
@W: BN132 :"d:\ppu_reverse\fpga\ppu_lite_lattice_v3\rp2c02_lite_lat_v3.v":1233:0:1233:5|Removing instance MOD_OBJ_EVAL.OBLATCH[2],  because it is equivalent to instance MOD_READBUSMUX.OB_R[2]
@W: BN132 :"d:\ppu_reverse\fpga\ppu_lite_lattice_v3\rp2c02_lite_lat_v3.v":1233:0:1233:5|Removing instance MOD_OBJ_EVAL.OBLATCH[1],  because it is equivalent to instance MOD_READBUSMUX.OB_R[1]
@W: BN132 :"d:\ppu_reverse\fpga\ppu_lite_lattice_v3\rp2c02_lite_lat_v3.v":1233:0:1233:5|Removing instance MOD_OBJ_EVAL.OBLATCH[0],  because it is equivalent to instance MOD_READBUSMUX.OB_R[0]
@W: BN132 :"d:\ppu_reverse\fpga\ppu_lite_lattice_v3\rp2c02_lite_lat_v3.v":1567:0:1567:5|Removing instance MOD_PIX_MUX.THO_LATCH[1],  because it is equivalent to instance MOD_BG_COLOR.THO1R
@W: BN132 :"d:\ppu_reverse\fpga\ppu_lite_lattice_v3\rp2c02_lite_lat_v3.v":1233:0:1233:5|Removing instance MOD_OBJ_EVAL.PDFIFO[1],  because it is equivalent to instance MOD_PAR_GEN.TAL_LATCH
@W: MT246 :"d:\ppu_reverse\fpga\ppu_lite_lattice_v3\pll.v":64:12:64:20|Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock RP2C02_LITE_LAT_V3|MCLK with period 1.54ns. Please declare a user-defined clock on object "p:MCLK"
@W: MT420 |Found inferred clock PLL|CLKOP_inferred_clock with period 6.24ns. Please declare a user-defined clock on object "n:MOD_PLL.CLKOP"
