@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N:: Running Verilog Compiler in System Verilog mode
@N:: Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"C:\lscc\diamond\3.5\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO
@N: CG364 :"C:\lscc\diamond\3.5\synpbase\lib\lucent\machxo2.v":1730:7:1730:13|Synthesizing module EHXPLLJ
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\PLL.v":8:7:8:9|Synthesizing module PLL
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":488:7:488:13|Synthesizing module CLK_DIV
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\CODER_NTSC_PAL.v":4:7:4:20|Synthesizing module CODER_NTSC_PAL
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":521:7:521:21|Synthesizing module REGISTER_SELECT
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":580:7:580:18|Synthesizing module REG2000_2001
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":645:7:645:16|Synthesizing module READBUSMUX
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":684:7:684:22|Synthesizing module TIMING_GENERATOR
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":897:7:897:23|Synthesizing module LOCAL_BUS_CONTROL
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":1510:7:1510:14|Synthesizing module SHIFTREG
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":956:7:956:14|Synthesizing module BG_COLOR
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":1641:7:1641:13|Synthesizing module COUNTER
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":1041:7:1041:13|Synthesizing module PAR_GEN
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":1197:7:1197:14|Synthesizing module OBJ_EVAL
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":1671:7:1671:17|Synthesizing module OAM_COUNTER
@N: CG364 :"C:\lscc\diamond\3.5\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI
@N: CG364 :"C:\lscc\diamond\3.5\synpbase\lib\lucent\machxo2.v":1291:7:1291:11|Synthesizing module DP8KC
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\OAM_RAM.v":8:7:8:13|Synthesizing module OAM_RAM
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\OAM2_RAM.v":8:7:8:14|Synthesizing module OAM2_RAM
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":1250:7:1250:9|Synthesizing module OAM
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":1475:7:1475:18|Synthesizing module FIFO_HPOSCNT
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":1348:7:1348:14|Synthesizing module OBJ_FIFO
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":1537:7:1537:13|Synthesizing module PIX_MUX
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\PALETTE_RAM.v":8:7:8:17|Synthesizing module PALETTE_RAM
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\PALETTE_RGB_TABLE.v":8:7:8:23|Synthesizing module PALETTE_RGB_TABLE
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":1588:7:1588:13|Synthesizing module PALETTE
@N: CG364 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":35:7:35:24|Synthesizing module RP2C02_LITE_LAT_V3
@N|Running in 64-bit mode
@N: NF107 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":35:7:35:24|Selected library: work cell: RP2C02_LITE_LAT_V3 view verilog as top level
@N: NF107 :"D:\PPU_REVERSE\FPGA\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":35:7:35:24|Selected library: work cell: RP2C02_LITE_LAT_V3 view verilog as top level

