@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled 
@N: BN362 :"d:\src\ppu_lite_lattice_v3\rp2c02_lite_lat_v3.v":507:0:507:5|Removing sequential instance SUBCLK of view:PrimLib.dff(prim) in hierarchy view:work.CLK_DIV(verilog) because there are no references to its outputs 
@N: BN362 :"d:\src\ppu_lite_lattice_v3\rp2c02_lite_lat_v3.v":507:0:507:5|Removing sequential instance SUB[1:0] of view:PrimLib.dff(prim) in hierarchy view:work.CLK_DIV(verilog) because there are no references to its outputs 
