@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled 
@N: BN362 :"d:\src\ppu_lite_lattice_v3\rp2c02_lite_lat_v3.v":815:0:815:5|Removing sequential instance RC in hierarchy view:work.TIMING_GENERATOR(verilog) because there are no references to its outputs 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
