@W: CG1249 :"D:\SRC\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":771:35:771:42|Redeclaration of implicit signal H_LINE23
@W: CL159 :"D:\SRC\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":47:6:47:11|Input VRAMCS is unused
@W: CL159 :"D:\SRC\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":48:6:48:12|Input VRAMA10 is unused
@W: CL159 :"D:\SRC\PPU_LITE_LATTICE_V3\RP2C02_LITE_LAT_V3.v":1571:6:1571:10|Input nPCLK is unused

