#--  Synopsys, Inc.
#--  Version J-2015.03L
#--  Project file D:\SRC\PPU_LITE_LATTICE_V3\based\run_options.txt
#--  Written on Thu Apr 16 21:36:42 2026


#project files
add_file -verilog "D:/SRC/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v"
add_file -verilog "D:/SRC/PPU_LITE_LATTICE_V3/PLL.v"
add_file -verilog "D:/SRC/PPU_LITE_LATTICE_V3/OAM_RAM.v"
add_file -verilog "D:/SRC/PPU_LITE_LATTICE_V3/OAM2_RAM.v"
add_file -verilog "D:/SRC/PPU_LITE_LATTICE_V3/PALETTE_RAM.v"
add_file -verilog "D:/SRC/PPU_LITE_LATTICE_V3/PALETTE_RGB_TABLE.v"
add_file -verilog "D:/SRC/PPU_LITE_LATTICE_V3/CODER_NTSC_PAL.v"



#implementation: "based"
impl -add based -type fpga

#
#implementation attributes

set_option -vlog_std v2001
set_option -project_relative_includes 1
set_option -include_path {D:/SRC/PPU_LITE_LATTICE_V3}

#device options
set_option -technology MACHXO2
set_option -part LCMXO2_1200HC
set_option -package TG100C
set_option -speed_grade -4
set_option -part_companion ""

#compilation/mapping options

# mapper_options
set_option -frequency 1
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1

# Lattice XP
set_option -maxfan 1000
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -pipe 1
set_option -forcegsr false
set_option -fix_gated_and_generated_clocks 1
set_option -rw_check_on_ram 1
set_option -update_models_cp 0
set_option -syn_edif_array_rename 1
set_option -Write_declared_clocks_only 1

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./PPU_LITE_LATTICE_V3_based.edi"

#set log file 
set_option log_file "D:/SRC/PPU_LITE_LATTICE_V3/based/PPU_LITE_LATTICE_V3_based.srf" 
impl -active "based"
