Setting log file to 'D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/based/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.5/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
(VERI-1482) Analyzing Verilog file D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(769,36-769,44) (VERI-1362) H_LINE23 is already implicitly declared on line 766
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1104,19-1104,22) (VERI-1875) identifier THZ is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1104,25-1104,29) (VERI-1875) identifier TVZB is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1105,19-1105,22) (VERI-1875) identifier TVZ is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1105,34-1105,38) (VERI-1875) identifier NTHC is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1106,34-1106,38) (VERI-1875) identifier NTVC is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1110,15-1110,18) (VERI-1875) identifier TVO is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1110,24-1110,27) (VERI-1875) identifier TVO is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1110,33-1110,36) (VERI-1875) identifier TVO is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1110,43-1110,46) (VERI-1875) identifier TVO is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1110,52-1110,55) (VERI-1875) identifier TVO is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1111,15-1111,18) (VERI-1875) identifier TVO is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1111,24-1111,27) (VERI-1875) identifier TVO is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1111,33-1111,36) (VERI-1875) identifier TVO is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1111,43-1111,46) (VERI-1875) identifier TVO is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1111,52-1111,55) (VERI-1875) identifier TVO is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1112,15-1112,18) (VERI-1875) identifier FVO is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1112,24-1112,27) (VERI-1875) identifier FVO is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1112,33-1112,36) (VERI-1875) identifier FVO is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1284,21-1284,25) (VERI-1875) identifier OAMQ is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1284,40-1284,47) (VERI-1875) identifier OAM1ADR is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1284,54-1284,61) (VERI-1875) identifier OAM1ADR is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1594,18-1594,19) (VERI-1875) identifier C is used before its declaration
WARNING - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1594,33-1594,37) (VERI-1875) identifier nB_W is used before its declaration
(VERI-1482) Analyzing Verilog file D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/PLL.v
(VERI-1482) Analyzing Verilog file D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/OAM_RAM.v
(VERI-1482) Analyzing Verilog file D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/OAM2_RAM.v
(VERI-1482) Analyzing Verilog file D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/PALETTE_RAM.v
(VERI-1482) Analyzing Verilog file D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/PALETTE_RGB_TABLE.v
(VERI-1482) Analyzing Verilog file D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/CODER_NTSC_PAL.v
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(35,8-35,26) (VERI-1018) compiling module RP2C02_LITE_LAT_V3
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(35,1-483,10) (VERI-9000) elaborating module 'RP2C02_LITE_LAT_V3'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/PLL.v(8,1-93,10) (VERI-9000) elaborating module 'PLL_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(488,1-515,10) (VERI-9000) elaborating module 'CLK_DIV_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/CODER_NTSC_PAL.v(4,1-118,10) (VERI-9000) elaborating module 'CODER_NTSC_PAL_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(520,1-574,10) (VERI-9000) elaborating module 'REGISTER_SELECT_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(579,1-639,10) (VERI-9000) elaborating module 'REG2000_2001_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(644,1-678,10) (VERI-9000) elaborating module 'READBUSMUX_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(683,1-887,10) (VERI-9000) elaborating module 'TIMING_GENERATOR_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(892,1-944,10) (VERI-9000) elaborating module 'LOCAL_BUS_CONTROL_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(949,1-1029,10) (VERI-9000) elaborating module 'BG_COLOR_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1034,1-1180,10) (VERI-9000) elaborating module 'PAR_GEN_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1185,1-1233,10) (VERI-9000) elaborating module 'OBJ_EVAL_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1238,1-1322,10) (VERI-9000) elaborating module 'OAM_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1327,1-1450,10) (VERI-9000) elaborating module 'OBJ_FIFO_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1516,1-1562,10) (VERI-9000) elaborating module 'PIX_MUX_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1567,1-1615,10) (VERI-9000) elaborating module 'PALETTE_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_3'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_4'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_5'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_6'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_7'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_8'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_9'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_10'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_11'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_12'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_13'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_14'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_15'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_16'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_17'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_18'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_19'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_20'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_21'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_22'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_23'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_24'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_25'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_26'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_27'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_28'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_29'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_30'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_31'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_32'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_33'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_34'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_35'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_36'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_37'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_38'
INFO - C:/lscc/diamond/3.5/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
INFO - C:/lscc/diamond/3.5/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1730,1-1786,10) (VERI-9000) elaborating module 'EHXPLLJ_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_2'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_3'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_4'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_5'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_6'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_7'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_8'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_9'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_10'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_11'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_12'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_13'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_14'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_15'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_16'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_17'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_18'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_19'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_20'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_21'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1489,1-1511,10) (VERI-9000) elaborating module 'SHIFTREG_uniq_22'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_2'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1651,1-1674,10) (VERI-9000) elaborating module 'OAM_COUNTER_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/OAM_RAM.v(8,1-96,10) (VERI-9000) elaborating module 'OAM_RAM_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/OAM2_RAM.v(8,1-96,10) (VERI-9000) elaborating module 'OAM2_RAM_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1455,1-1484,10) (VERI-9000) elaborating module 'FIFO_HPOSCNT_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1455,1-1484,10) (VERI-9000) elaborating module 'FIFO_HPOSCNT_uniq_2'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1455,1-1484,10) (VERI-9000) elaborating module 'FIFO_HPOSCNT_uniq_3'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1455,1-1484,10) (VERI-9000) elaborating module 'FIFO_HPOSCNT_uniq_4'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1455,1-1484,10) (VERI-9000) elaborating module 'FIFO_HPOSCNT_uniq_5'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1455,1-1484,10) (VERI-9000) elaborating module 'FIFO_HPOSCNT_uniq_6'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1455,1-1484,10) (VERI-9000) elaborating module 'FIFO_HPOSCNT_uniq_7'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1455,1-1484,10) (VERI-9000) elaborating module 'FIFO_HPOSCNT_uniq_8'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/PALETTE_RAM.v(8,1-96,10) (VERI-9000) elaborating module 'PALETTE_RAM_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/PALETTE_RGB_TABLE.v(8,1-95,10) (VERI-9000) elaborating module 'PALETTE_RGB_TABLE_uniq_1'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_39'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_40'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_41'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_42'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_43'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_44'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_45'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_46'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_47'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_48'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_49'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_50'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_51'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_52'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_53'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_54'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_55'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_56'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_57'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_58'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_59'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_60'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_61'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_62'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_63'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_64'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_65'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_66'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_67'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_68'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_69'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_70'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_71'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_72'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_73'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_74'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_75'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_76'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_77'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_78'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_79'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_80'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_81'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_82'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_83'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_84'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_85'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_86'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_87'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_88'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_89'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_90'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_91'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_92'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_93'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_94'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_95'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_96'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_97'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_98'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_99'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_100'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_101'
INFO - D:/PPU_REVERSE/FPGA/PPU_LITE_LATTICE_V3/RP2C02_LITE_LAT_V3.v(1620,1-1646,10) (VERI-9000) elaborating module 'COUNTER_uniq_102'
INFO - C:/lscc/diamond/3.5/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_2'
INFO - C:/lscc/diamond/3.5/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_3'
INFO - C:/lscc/diamond/3.5/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_4'
INFO - C:/lscc/diamond/3.5/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_5'
INFO - C:/lscc/diamond/3.5/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
INFO - C:/lscc/diamond/3.5/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_2'
INFO - C:/lscc/diamond/3.5/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_3'
INFO - C:/lscc/diamond/3.5/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_4'
INFO - C:/lscc/diamond/3.5/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_1'
INFO - C:/lscc/diamond/3.5/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_2'
INFO - C:/lscc/diamond/3.5/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_3'
INFO - C:/lscc/diamond/3.5/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_4'
Done: design load finished with (0) errors, and (24) warnings