Place & Route TRACE Report
Loading design for application trce from file ppu_lite_lattice_v3_based.ncd.
Design name: RP2C02_LITE_LAT_V3
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.5/ispfpga.
Package Status: Final Version 1.41.
Performance Hardware Data Status: Final Version 30.4.
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond Version 3.5.0.102
Thu Apr 16 21:37:18 2026
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2015 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o PPU_LITE_LATTICE_V3_based.twr -gui -msgset D:/SRC/PPU_LITE_LATTICE_V3/promote.xml PPU_LITE_LATTICE_V3_based.ncd PPU_LITE_LATTICE_V3_based.prf
Design file: ppu_lite_lattice_v3_based.ncd
Preference file: ppu_lite_lattice_v3_based.prf
Device,speed: LCMXO2-1200HC,4
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "MCLK_c" 21.477000 MHz (0 errors) 5 items scored, 0 timing errors detected.
Report: 213.493MHz is the maximum frequency for this preference.
FREQUENCY NET "Clk" 42.954000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
Report: 71.500MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "MCLK_c" 21.477000 MHz ;
5 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 20.938ns (weighted slack = 41.876ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_CLK_DIV/DIV[1] (from MCLK_c +)
Destination: FF Data in MOD_CLK_DIV/DIV2n (to MCLK_c -)
Delay: 1.456ns (31.0% logic, 69.0% route), 1 logic levels.
Constraint Details:
1.456ns physical path delay MOD_CLK_DIV/SLICE_88 to SLICE_775 meets
23.281ns delay constraint less
0.539ns skew and
0.348ns M_SET requirement (totaling 22.394ns) by 20.938ns
Physical Path Details:
Data path MOD_CLK_DIV/SLICE_88 to SLICE_775:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C12D.CLK to R7C12D.Q1 MOD_CLK_DIV/SLICE_88 (from MCLK_c)
ROUTE 5 1.004 R7C12D.Q1 to R8C12D.M0 MOD_CLK_DIV/DIV[1] (to MCLK_c)
--------
1.456 (31.0% logic, 69.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path MCLK to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 4 2.614 34.PADDI to R7C12D.CLK MCLK_c
--------
2.614 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MCLK to SLICE_775:
Name Fanout Delay (ns) Site Resource
ROUTE 4 2.075 34.PADDI to R8C12D.CLK MCLK_c
--------
2.075 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 43.866ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_CLK_DIV/DIV[1] (from MCLK_c +)
Destination: FF Data in MOD_CLK_DIV/DIV[2] (to MCLK_c +)
Delay: 1.990ns (47.6% logic, 52.4% route), 2 logic levels.
Constraint Details:
1.990ns physical path delay MOD_CLK_DIV/SLICE_88 to SLICE_89 meets
46.561ns delay constraint less
0.539ns skew and
0.166ns DIN_SET requirement (totaling 45.856ns) by 43.866ns
Physical Path Details:
Data path MOD_CLK_DIV/SLICE_88 to SLICE_89:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C12D.CLK to R7C12D.Q1 MOD_CLK_DIV/SLICE_88 (from MCLK_c)
ROUTE 5 1.043 R7C12D.Q1 to R8C12A.B0 MOD_CLK_DIV/DIV[1]
CTOF_DEL --- 0.495 R8C12A.B0 to R8C12A.F0 SLICE_89
ROUTE 1 0.000 R8C12A.F0 to R8C12A.DI0 MOD_CLK_DIV/DIV2n_2 (to MCLK_c)
--------
1.990 (47.6% logic, 52.4% route), 2 logic levels.
Clock Skew Details:
Source Clock Path MCLK to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 4 2.614 34.PADDI to R7C12D.CLK MCLK_c
--------
2.614 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MCLK to SLICE_89:
Name Fanout Delay (ns) Site Resource
ROUTE 4 2.075 34.PADDI to R8C12A.CLK MCLK_c
--------
2.075 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 44.359ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_CLK_DIV/DIV[0] (from MCLK_c +)
Destination: FF Data in MOD_CLK_DIV/DIV[1] (to MCLK_c +)
Delay: 1.854ns (24.4% logic, 75.6% route), 1 logic levels.
Constraint Details:
1.854ns physical path delay MOD_CLK_DIV/SLICE_88 to MOD_CLK_DIV/SLICE_88 meets
46.561ns delay constraint less
0.000ns skew and
0.348ns M_SET requirement (totaling 46.213ns) by 44.359ns
Physical Path Details:
Data path MOD_CLK_DIV/SLICE_88 to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C12D.CLK to R7C12D.Q0 MOD_CLK_DIV/SLICE_88 (from MCLK_c)
ROUTE 1 1.402 R7C12D.Q0 to R7C12D.M1 MOD_CLK_DIV/DIV[0] (to MCLK_c)
--------
1.854 (24.4% logic, 75.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path MCLK to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 4 2.614 34.PADDI to R7C12D.CLK MCLK_c
--------
2.614 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MCLK to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 4 2.614 34.PADDI to R7C12D.CLK MCLK_c
--------
2.614 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 44.453ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_CLK_DIV/DIV[1] (from MCLK_c +)
Destination: FF Data in MOD_CLK_DIV/DIV[0] (to MCLK_c +)
Delay: 1.942ns (48.8% logic, 51.2% route), 2 logic levels.
Constraint Details:
1.942ns physical path delay MOD_CLK_DIV/SLICE_88 to MOD_CLK_DIV/SLICE_88 meets
46.561ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 46.395ns) by 44.453ns
Physical Path Details:
Data path MOD_CLK_DIV/SLICE_88 to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C12D.CLK to R7C12D.Q1 MOD_CLK_DIV/SLICE_88 (from MCLK_c)
ROUTE 5 0.995 R7C12D.Q1 to R7C12D.A0 MOD_CLK_DIV/DIV[1]
CTOF_DEL --- 0.495 R7C12D.A0 to R7C12D.F0 MOD_CLK_DIV/SLICE_88
ROUTE 1 0.000 R7C12D.F0 to R7C12D.DI0 MOD_CLK_DIV/un2_DIV_i (to MCLK_c)
--------
1.942 (48.8% logic, 51.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path MCLK to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 4 2.614 34.PADDI to R7C12D.CLK MCLK_c
--------
2.614 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MCLK to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 4 2.614 34.PADDI to R7C12D.CLK MCLK_c
--------
2.614 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 45.264ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_CLK_DIV/DIV[2] (from MCLK_c +)
Destination: FF Data in MOD_CLK_DIV/DIV[0] (to MCLK_c +)
Delay: 1.670ns (56.7% logic, 43.3% route), 2 logic levels.
Constraint Details:
1.670ns physical path delay SLICE_89 to MOD_CLK_DIV/SLICE_88 meets
46.561ns delay constraint less
-0.539ns skew and
0.166ns DIN_SET requirement (totaling 46.934ns) by 45.264ns
Physical Path Details:
Data path SLICE_89 to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R8C12A.CLK to R8C12A.Q0 SLICE_89 (from MCLK_c)
ROUTE 3 0.723 R8C12A.Q0 to R7C12D.D0 MOD_CLK_DIV/DIV[2]
CTOF_DEL --- 0.495 R7C12D.D0 to R7C12D.F0 MOD_CLK_DIV/SLICE_88
ROUTE 1 0.000 R7C12D.F0 to R7C12D.DI0 MOD_CLK_DIV/un2_DIV_i (to MCLK_c)
--------
1.670 (56.7% logic, 43.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path MCLK to SLICE_89:
Name Fanout Delay (ns) Site Resource
ROUTE 4 2.075 34.PADDI to R8C12A.CLK MCLK_c
--------
2.075 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MCLK to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 4 2.614 34.PADDI to R7C12D.CLK MCLK_c
--------
2.614 (0.0% logic, 100.0% route), 0 logic levels.
Report: 213.493MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "Clk" 42.954000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 9.295ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_TIMING_GENERATOR/VCNT[4]/CNT (from Clk +)
Destination: FF Data in MOD_OAM/OAMCNT/CNT1[7] (to Clk +)
Delay: 13.820ns (39.4% logic, 60.6% route), 10 logic levels.
Constraint Details:
13.820ns physical path delay MOD_TIMING_GENERATOR/SLICE_654 to SLICE_125 meets
23.281ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 23.115ns) by 9.295ns
Physical Path Details:
Data path MOD_TIMING_GENERATOR/SLICE_654 to SLICE_125:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R10C13B.CLK to R10C13B.Q0 MOD_TIMING_GENERATOR/SLICE_654 (from Clk)
ROUTE 9 2.441 R10C13B.Q0 to R9C8C.A1 Vo[4]
C1TOFCO_DE --- 0.889 R9C8C.A1 to R9C8C.FCO SLICE_3
ROUTE 1 0.000 R9C8C.FCO to R9C8D.FCI MOD_OBJ_EVAL/OVS_cry_4
FCITOF1_DE --- 0.643 R9C8D.FCI to R9C8D.F1 SLICE_2
ROUTE 1 1.450 R9C8D.F1 to R7C6A.B0 MOD_OBJ_EVAL/OVS[6]
CTOF_DEL --- 0.495 R7C6A.B0 to R7C6A.F0 SLICE_650
ROUTE 2 0.637 R7C6A.F0 to R7C7D.D1 MOD_OBJ_EVAL/m4_4
CTOF_DEL --- 0.495 R7C7D.D1 to R7C7D.F1 MOD_OBJ_EVAL/SLICE_148
ROUTE 1 0.436 R7C7D.F1 to R7C7D.C0 MOD_OBJ_EVAL/N_41_mux
CTOF_DEL --- 0.495 R7C7D.C0 to R7C7D.F0 MOD_OBJ_EVAL/SLICE_148
ROUTE 5 1.205 R7C7D.F0 to R4C6A.D0 MOD_OBJ_EVAL/un1_DO_COPY_i_0
CTOF_DEL --- 0.495 R4C6A.D0 to R4C6A.F0 SLICE_131
ROUTE 4 1.096 R4C6A.F0 to R5C5D.D1 N_45_mux
CTOF_DEL --- 0.495 R5C5D.D1 to R5C5D.F1 SLICE_705
ROUTE 4 0.445 R5C5D.F1 to R5C5D.C0 MOD_OBJ_EVAL/N_26
CTOF_DEL --- 0.495 R5C5D.C0 to R5C5D.F0 SLICE_705
ROUTE 3 0.661 R5C5D.F0 to R5C4A.D1 MOD_OBJ_EVAL/N_29
CTOF_DEL --- 0.495 R5C4A.D1 to R5C4A.F1 SLICE_125
ROUTE 1 0.000 R5C4A.F1 to R5C4A.DI1 N_32_i_0 (to Clk)
--------
13.820 (39.4% logic, 60.6% route), 10 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to MOD_TIMING_GENERATOR/SLICE_654:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R10C13B.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to SLICE_125:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R5C4A.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.295ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_TIMING_GENERATOR/VCNT[4]/CNT (from Clk +)
Destination: FF Data in MOD_OAM/OAMCNT/CNT1[6] (to Clk +)
Delay: 13.820ns (39.4% logic, 60.6% route), 10 logic levels.
Constraint Details:
13.820ns physical path delay MOD_TIMING_GENERATOR/SLICE_654 to SLICE_125 meets
23.281ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 23.115ns) by 9.295ns
Physical Path Details:
Data path MOD_TIMING_GENERATOR/SLICE_654 to SLICE_125:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R10C13B.CLK to R10C13B.Q0 MOD_TIMING_GENERATOR/SLICE_654 (from Clk)
ROUTE 9 2.441 R10C13B.Q0 to R9C8C.A1 Vo[4]
C1TOFCO_DE --- 0.889 R9C8C.A1 to R9C8C.FCO SLICE_3
ROUTE 1 0.000 R9C8C.FCO to R9C8D.FCI MOD_OBJ_EVAL/OVS_cry_4
FCITOF1_DE --- 0.643 R9C8D.FCI to R9C8D.F1 SLICE_2
ROUTE 1 1.450 R9C8D.F1 to R7C6A.B0 MOD_OBJ_EVAL/OVS[6]
CTOF_DEL --- 0.495 R7C6A.B0 to R7C6A.F0 SLICE_650
ROUTE 2 0.637 R7C6A.F0 to R7C7D.D1 MOD_OBJ_EVAL/m4_4
CTOF_DEL --- 0.495 R7C7D.D1 to R7C7D.F1 MOD_OBJ_EVAL/SLICE_148
ROUTE 1 0.436 R7C7D.F1 to R7C7D.C0 MOD_OBJ_EVAL/N_41_mux
CTOF_DEL --- 0.495 R7C7D.C0 to R7C7D.F0 MOD_OBJ_EVAL/SLICE_148
ROUTE 5 1.205 R7C7D.F0 to R4C6A.D0 MOD_OBJ_EVAL/un1_DO_COPY_i_0
CTOF_DEL --- 0.495 R4C6A.D0 to R4C6A.F0 SLICE_131
ROUTE 4 1.096 R4C6A.F0 to R5C5D.D1 N_45_mux
CTOF_DEL --- 0.495 R5C5D.D1 to R5C5D.F1 SLICE_705
ROUTE 4 0.445 R5C5D.F1 to R5C5D.C0 MOD_OBJ_EVAL/N_26
CTOF_DEL --- 0.495 R5C5D.C0 to R5C5D.F0 SLICE_705
ROUTE 3 0.661 R5C5D.F0 to R5C4A.D0 MOD_OBJ_EVAL/N_29
CTOF_DEL --- 0.495 R5C4A.D0 to R5C4A.F0 SLICE_125
ROUTE 1 0.000 R5C4A.F0 to R5C4A.DI0 N_33_i_0 (to Clk)
--------
13.820 (39.4% logic, 60.6% route), 10 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to MOD_TIMING_GENERATOR/SLICE_654:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R10C13B.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to SLICE_125:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R5C4A.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.324ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_TIMING_GENERATOR/VCNT[4]/CNT (from Clk +)
Destination: FF Data in MOD_OAM/OAMCNT/CNT1[5] (to Clk +)
Delay: 13.791ns (39.5% logic, 60.5% route), 10 logic levels.
Constraint Details:
13.791ns physical path delay MOD_TIMING_GENERATOR/SLICE_654 to SLICE_124 meets
23.281ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 23.115ns) by 9.324ns
Physical Path Details:
Data path MOD_TIMING_GENERATOR/SLICE_654 to SLICE_124:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R10C13B.CLK to R10C13B.Q0 MOD_TIMING_GENERATOR/SLICE_654 (from Clk)
ROUTE 9 2.441 R10C13B.Q0 to R9C8C.A1 Vo[4]
C1TOFCO_DE --- 0.889 R9C8C.A1 to R9C8C.FCO SLICE_3
ROUTE 1 0.000 R9C8C.FCO to R9C8D.FCI MOD_OBJ_EVAL/OVS_cry_4
FCITOF1_DE --- 0.643 R9C8D.FCI to R9C8D.F1 SLICE_2
ROUTE 1 1.450 R9C8D.F1 to R7C6A.B0 MOD_OBJ_EVAL/OVS[6]
CTOF_DEL --- 0.495 R7C6A.B0 to R7C6A.F0 SLICE_650
ROUTE 2 0.637 R7C6A.F0 to R7C7D.D1 MOD_OBJ_EVAL/m4_4
CTOF_DEL --- 0.495 R7C7D.D1 to R7C7D.F1 MOD_OBJ_EVAL/SLICE_148
ROUTE 1 0.436 R7C7D.F1 to R7C7D.C0 MOD_OBJ_EVAL/N_41_mux
CTOF_DEL --- 0.495 R7C7D.C0 to R7C7D.F0 MOD_OBJ_EVAL/SLICE_148
ROUTE 5 1.205 R7C7D.F0 to R4C6A.D0 MOD_OBJ_EVAL/un1_DO_COPY_i_0
CTOF_DEL --- 0.495 R4C6A.D0 to R4C6A.F0 SLICE_131
ROUTE 4 1.096 R4C6A.F0 to R5C5D.D1 N_45_mux
CTOF_DEL --- 0.495 R5C5D.D1 to R5C5D.F1 SLICE_705
ROUTE 4 0.445 R5C5D.F1 to R5C5D.C0 MOD_OBJ_EVAL/N_26
CTOF_DEL --- 0.495 R5C5D.C0 to R5C5D.F0 SLICE_705
ROUTE 3 0.632 R5C5D.F0 to R5C4D.D1 MOD_OBJ_EVAL/N_29
CTOF_DEL --- 0.495 R5C4D.D1 to R5C4D.F1 SLICE_124
ROUTE 1 0.000 R5C4D.F1 to R5C4D.DI1 N_34_i_0 (to Clk)
--------
13.791 (39.5% logic, 60.5% route), 10 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to MOD_TIMING_GENERATOR/SLICE_654:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R10C13B.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to SLICE_124:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R5C4D.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.463ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_READBUSMUX/OB_R[4] (from Clk +)
Destination: FF Data in MOD_OAM/OAMCNT/CNT1[7] (to Clk +)
Delay: 13.652ns (39.9% logic, 60.1% route), 10 logic levels.
Constraint Details:
13.652ns physical path delay SLICE_11 to SLICE_125 meets
23.281ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 23.115ns) by 9.463ns
Physical Path Details:
Data path SLICE_11 to SLICE_125:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R10C17D.CLK to R10C17D.Q1 SLICE_11 (from Clk)
ROUTE 2 2.273 R10C17D.Q1 to R9C8C.B1 MOD_READBUSMUX.OB_R[4]
C1TOFCO_DE --- 0.889 R9C8C.B1 to R9C8C.FCO SLICE_3
ROUTE 1 0.000 R9C8C.FCO to R9C8D.FCI MOD_OBJ_EVAL/OVS_cry_4
FCITOF1_DE --- 0.643 R9C8D.FCI to R9C8D.F1 SLICE_2
ROUTE 1 1.450 R9C8D.F1 to R7C6A.B0 MOD_OBJ_EVAL/OVS[6]
CTOF_DEL --- 0.495 R7C6A.B0 to R7C6A.F0 SLICE_650
ROUTE 2 0.637 R7C6A.F0 to R7C7D.D1 MOD_OBJ_EVAL/m4_4
CTOF_DEL --- 0.495 R7C7D.D1 to R7C7D.F1 MOD_OBJ_EVAL/SLICE_148
ROUTE 1 0.436 R7C7D.F1 to R7C7D.C0 MOD_OBJ_EVAL/N_41_mux
CTOF_DEL --- 0.495 R7C7D.C0 to R7C7D.F0 MOD_OBJ_EVAL/SLICE_148
ROUTE 5 1.205 R7C7D.F0 to R4C6A.D0 MOD_OBJ_EVAL/un1_DO_COPY_i_0
CTOF_DEL --- 0.495 R4C6A.D0 to R4C6A.F0 SLICE_131
ROUTE 4 1.096 R4C6A.F0 to R5C5D.D1 N_45_mux
CTOF_DEL --- 0.495 R5C5D.D1 to R5C5D.F1 SLICE_705
ROUTE 4 0.445 R5C5D.F1 to R5C5D.C0 MOD_OBJ_EVAL/N_26
CTOF_DEL --- 0.495 R5C5D.C0 to R5C5D.F0 SLICE_705
ROUTE 3 0.661 R5C5D.F0 to R5C4A.D1 MOD_OBJ_EVAL/N_29
CTOF_DEL --- 0.495 R5C4A.D1 to R5C4A.F1 SLICE_125
ROUTE 1 0.000 R5C4A.F1 to R5C4A.DI1 N_32_i_0 (to Clk)
--------
13.652 (39.9% logic, 60.1% route), 10 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to SLICE_11:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R10C17D.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to SLICE_125:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R5C4A.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.463ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_READBUSMUX/OB_R[4] (from Clk +)
Destination: FF Data in MOD_OAM/OAMCNT/CNT1[6] (to Clk +)
Delay: 13.652ns (39.9% logic, 60.1% route), 10 logic levels.
Constraint Details:
13.652ns physical path delay SLICE_11 to SLICE_125 meets
23.281ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 23.115ns) by 9.463ns
Physical Path Details:
Data path SLICE_11 to SLICE_125:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R10C17D.CLK to R10C17D.Q1 SLICE_11 (from Clk)
ROUTE 2 2.273 R10C17D.Q1 to R9C8C.B1 MOD_READBUSMUX.OB_R[4]
C1TOFCO_DE --- 0.889 R9C8C.B1 to R9C8C.FCO SLICE_3
ROUTE 1 0.000 R9C8C.FCO to R9C8D.FCI MOD_OBJ_EVAL/OVS_cry_4
FCITOF1_DE --- 0.643 R9C8D.FCI to R9C8D.F1 SLICE_2
ROUTE 1 1.450 R9C8D.F1 to R7C6A.B0 MOD_OBJ_EVAL/OVS[6]
CTOF_DEL --- 0.495 R7C6A.B0 to R7C6A.F0 SLICE_650
ROUTE 2 0.637 R7C6A.F0 to R7C7D.D1 MOD_OBJ_EVAL/m4_4
CTOF_DEL --- 0.495 R7C7D.D1 to R7C7D.F1 MOD_OBJ_EVAL/SLICE_148
ROUTE 1 0.436 R7C7D.F1 to R7C7D.C0 MOD_OBJ_EVAL/N_41_mux
CTOF_DEL --- 0.495 R7C7D.C0 to R7C7D.F0 MOD_OBJ_EVAL/SLICE_148
ROUTE 5 1.205 R7C7D.F0 to R4C6A.D0 MOD_OBJ_EVAL/un1_DO_COPY_i_0
CTOF_DEL --- 0.495 R4C6A.D0 to R4C6A.F0 SLICE_131
ROUTE 4 1.096 R4C6A.F0 to R5C5D.D1 N_45_mux
CTOF_DEL --- 0.495 R5C5D.D1 to R5C5D.F1 SLICE_705
ROUTE 4 0.445 R5C5D.F1 to R5C5D.C0 MOD_OBJ_EVAL/N_26
CTOF_DEL --- 0.495 R5C5D.C0 to R5C5D.F0 SLICE_705
ROUTE 3 0.661 R5C5D.F0 to R5C4A.D0 MOD_OBJ_EVAL/N_29
CTOF_DEL --- 0.495 R5C4A.D0 to R5C4A.F0 SLICE_125
ROUTE 1 0.000 R5C4A.F0 to R5C4A.DI0 N_33_i_0 (to Clk)
--------
13.652 (39.9% logic, 60.1% route), 10 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to SLICE_11:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R10C17D.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to SLICE_125:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R5C4A.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.492ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_READBUSMUX/OB_R[4] (from Clk +)
Destination: FF Data in MOD_OAM/OAMCNT/CNT1[5] (to Clk +)
Delay: 13.623ns (40.0% logic, 60.0% route), 10 logic levels.
Constraint Details:
13.623ns physical path delay SLICE_11 to SLICE_124 meets
23.281ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 23.115ns) by 9.492ns
Physical Path Details:
Data path SLICE_11 to SLICE_124:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R10C17D.CLK to R10C17D.Q1 SLICE_11 (from Clk)
ROUTE 2 2.273 R10C17D.Q1 to R9C8C.B1 MOD_READBUSMUX.OB_R[4]
C1TOFCO_DE --- 0.889 R9C8C.B1 to R9C8C.FCO SLICE_3
ROUTE 1 0.000 R9C8C.FCO to R9C8D.FCI MOD_OBJ_EVAL/OVS_cry_4
FCITOF1_DE --- 0.643 R9C8D.FCI to R9C8D.F1 SLICE_2
ROUTE 1 1.450 R9C8D.F1 to R7C6A.B0 MOD_OBJ_EVAL/OVS[6]
CTOF_DEL --- 0.495 R7C6A.B0 to R7C6A.F0 SLICE_650
ROUTE 2 0.637 R7C6A.F0 to R7C7D.D1 MOD_OBJ_EVAL/m4_4
CTOF_DEL --- 0.495 R7C7D.D1 to R7C7D.F1 MOD_OBJ_EVAL/SLICE_148
ROUTE 1 0.436 R7C7D.F1 to R7C7D.C0 MOD_OBJ_EVAL/N_41_mux
CTOF_DEL --- 0.495 R7C7D.C0 to R7C7D.F0 MOD_OBJ_EVAL/SLICE_148
ROUTE 5 1.205 R7C7D.F0 to R4C6A.D0 MOD_OBJ_EVAL/un1_DO_COPY_i_0
CTOF_DEL --- 0.495 R4C6A.D0 to R4C6A.F0 SLICE_131
ROUTE 4 1.096 R4C6A.F0 to R5C5D.D1 N_45_mux
CTOF_DEL --- 0.495 R5C5D.D1 to R5C5D.F1 SLICE_705
ROUTE 4 0.445 R5C5D.F1 to R5C5D.C0 MOD_OBJ_EVAL/N_26
CTOF_DEL --- 0.495 R5C5D.C0 to R5C5D.F0 SLICE_705
ROUTE 3 0.632 R5C5D.F0 to R5C4D.D1 MOD_OBJ_EVAL/N_29
CTOF_DEL --- 0.495 R5C4D.D1 to R5C4D.F1 SLICE_124
ROUTE 1 0.000 R5C4D.F1 to R5C4D.DI1 N_34_i_0 (to Clk)
--------
13.623 (40.0% logic, 60.0% route), 10 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to SLICE_11:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R10C17D.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to SLICE_124:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R5C4D.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.555ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_TIMING_GENERATOR/VCNT[0]/CNT (from Clk +)
Destination: FF Data in MOD_OAM/OAMCNT/CNT1[6] (to Clk +)
Delay: 13.560ns (42.6% logic, 57.4% route), 12 logic levels.
Constraint Details:
13.560ns physical path delay MOD_TIMING_GENERATOR/SLICE_652 to SLICE_125 meets
23.281ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 23.115ns) by 9.555ns
Physical Path Details:
Data path MOD_TIMING_GENERATOR/SLICE_652 to SLICE_125:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R10C15A.CLK to R10C15A.Q0 MOD_TIMING_GENERATOR/SLICE_652 (from Clk)
ROUTE 14 1.857 R10C15A.Q0 to R9C8A.A1 Vo[0]
C1TOFCO_DE --- 0.889 R9C8A.A1 to R9C8A.FCO SLICE_0
ROUTE 1 0.000 R9C8A.FCO to R9C8B.FCI MOD_OBJ_EVAL/OVS_cry_0
FCITOFCO_D --- 0.162 R9C8B.FCI to R9C8B.FCO SLICE_4
ROUTE 1 0.000 R9C8B.FCO to R9C8C.FCI MOD_OBJ_EVAL/OVS_cry_2
FCITOFCO_D --- 0.162 R9C8C.FCI to R9C8C.FCO SLICE_3
ROUTE 1 0.000 R9C8C.FCO to R9C8D.FCI MOD_OBJ_EVAL/OVS_cry_4
FCITOF1_DE --- 0.643 R9C8D.FCI to R9C8D.F1 SLICE_2
ROUTE 1 1.450 R9C8D.F1 to R7C6A.B0 MOD_OBJ_EVAL/OVS[6]
CTOF_DEL --- 0.495 R7C6A.B0 to R7C6A.F0 SLICE_650
ROUTE 2 0.637 R7C6A.F0 to R7C7D.D1 MOD_OBJ_EVAL/m4_4
CTOF_DEL --- 0.495 R7C7D.D1 to R7C7D.F1 MOD_OBJ_EVAL/SLICE_148
ROUTE 1 0.436 R7C7D.F1 to R7C7D.C0 MOD_OBJ_EVAL/N_41_mux
CTOF_DEL --- 0.495 R7C7D.C0 to R7C7D.F0 MOD_OBJ_EVAL/SLICE_148
ROUTE 5 1.205 R7C7D.F0 to R4C6A.D0 MOD_OBJ_EVAL/un1_DO_COPY_i_0
CTOF_DEL --- 0.495 R4C6A.D0 to R4C6A.F0 SLICE_131
ROUTE 4 1.096 R4C6A.F0 to R5C5D.D1 N_45_mux
CTOF_DEL --- 0.495 R5C5D.D1 to R5C5D.F1 SLICE_705
ROUTE 4 0.445 R5C5D.F1 to R5C5D.C0 MOD_OBJ_EVAL/N_26
CTOF_DEL --- 0.495 R5C5D.C0 to R5C5D.F0 SLICE_705
ROUTE 3 0.661 R5C5D.F0 to R5C4A.D0 MOD_OBJ_EVAL/N_29
CTOF_DEL --- 0.495 R5C4A.D0 to R5C4A.F0 SLICE_125
ROUTE 1 0.000 R5C4A.F0 to R5C4A.DI0 N_33_i_0 (to Clk)
--------
13.560 (42.6% logic, 57.4% route), 12 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to MOD_TIMING_GENERATOR/SLICE_652:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R10C15A.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to SLICE_125:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R5C4A.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.555ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_TIMING_GENERATOR/VCNT[0]/CNT (from Clk +)
Destination: FF Data in MOD_OAM/OAMCNT/CNT1[7] (to Clk +)
Delay: 13.560ns (42.6% logic, 57.4% route), 12 logic levels.
Constraint Details:
13.560ns physical path delay MOD_TIMING_GENERATOR/SLICE_652 to SLICE_125 meets
23.281ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 23.115ns) by 9.555ns
Physical Path Details:
Data path MOD_TIMING_GENERATOR/SLICE_652 to SLICE_125:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R10C15A.CLK to R10C15A.Q0 MOD_TIMING_GENERATOR/SLICE_652 (from Clk)
ROUTE 14 1.857 R10C15A.Q0 to R9C8A.A1 Vo[0]
C1TOFCO_DE --- 0.889 R9C8A.A1 to R9C8A.FCO SLICE_0
ROUTE 1 0.000 R9C8A.FCO to R9C8B.FCI MOD_OBJ_EVAL/OVS_cry_0
FCITOFCO_D --- 0.162 R9C8B.FCI to R9C8B.FCO SLICE_4
ROUTE 1 0.000 R9C8B.FCO to R9C8C.FCI MOD_OBJ_EVAL/OVS_cry_2
FCITOFCO_D --- 0.162 R9C8C.FCI to R9C8C.FCO SLICE_3
ROUTE 1 0.000 R9C8C.FCO to R9C8D.FCI MOD_OBJ_EVAL/OVS_cry_4
FCITOF1_DE --- 0.643 R9C8D.FCI to R9C8D.F1 SLICE_2
ROUTE 1 1.450 R9C8D.F1 to R7C6A.B0 MOD_OBJ_EVAL/OVS[6]
CTOF_DEL --- 0.495 R7C6A.B0 to R7C6A.F0 SLICE_650
ROUTE 2 0.637 R7C6A.F0 to R7C7D.D1 MOD_OBJ_EVAL/m4_4
CTOF_DEL --- 0.495 R7C7D.D1 to R7C7D.F1 MOD_OBJ_EVAL/SLICE_148
ROUTE 1 0.436 R7C7D.F1 to R7C7D.C0 MOD_OBJ_EVAL/N_41_mux
CTOF_DEL --- 0.495 R7C7D.C0 to R7C7D.F0 MOD_OBJ_EVAL/SLICE_148
ROUTE 5 1.205 R7C7D.F0 to R4C6A.D0 MOD_OBJ_EVAL/un1_DO_COPY_i_0
CTOF_DEL --- 0.495 R4C6A.D0 to R4C6A.F0 SLICE_131
ROUTE 4 1.096 R4C6A.F0 to R5C5D.D1 N_45_mux
CTOF_DEL --- 0.495 R5C5D.D1 to R5C5D.F1 SLICE_705
ROUTE 4 0.445 R5C5D.F1 to R5C5D.C0 MOD_OBJ_EVAL/N_26
CTOF_DEL --- 0.495 R5C5D.C0 to R5C5D.F0 SLICE_705
ROUTE 3 0.661 R5C5D.F0 to R5C4A.D1 MOD_OBJ_EVAL/N_29
CTOF_DEL --- 0.495 R5C4A.D1 to R5C4A.F1 SLICE_125
ROUTE 1 0.000 R5C4A.F1 to R5C4A.DI1 N_32_i_0 (to Clk)
--------
13.560 (42.6% logic, 57.4% route), 12 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to MOD_TIMING_GENERATOR/SLICE_652:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R10C15A.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to SLICE_125:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R5C4A.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.566ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_READBUSMUX/OB_R[0] (from Clk +)
Destination: FF Data in MOD_OAM/OAMCNT/CNT1[7] (to Clk +)
Delay: 13.549ns (42.6% logic, 57.4% route), 12 logic levels.
Constraint Details:
13.549ns physical path delay SLICE_556 to SLICE_125 meets
23.281ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 23.115ns) by 9.566ns
Physical Path Details:
Data path SLICE_556 to SLICE_125:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R9C15B.CLK to R9C15B.Q1 SLICE_556 (from Clk)
ROUTE 3 1.846 R9C15B.Q1 to R9C8A.B1 MOD_READBUSMUX.OB_R[0]
C1TOFCO_DE --- 0.889 R9C8A.B1 to R9C8A.FCO SLICE_0
ROUTE 1 0.000 R9C8A.FCO to R9C8B.FCI MOD_OBJ_EVAL/OVS_cry_0
FCITOFCO_D --- 0.162 R9C8B.FCI to R9C8B.FCO SLICE_4
ROUTE 1 0.000 R9C8B.FCO to R9C8C.FCI MOD_OBJ_EVAL/OVS_cry_2
FCITOFCO_D --- 0.162 R9C8C.FCI to R9C8C.FCO SLICE_3
ROUTE 1 0.000 R9C8C.FCO to R9C8D.FCI MOD_OBJ_EVAL/OVS_cry_4
FCITOF1_DE --- 0.643 R9C8D.FCI to R9C8D.F1 SLICE_2
ROUTE 1 1.450 R9C8D.F1 to R7C6A.B0 MOD_OBJ_EVAL/OVS[6]
CTOF_DEL --- 0.495 R7C6A.B0 to R7C6A.F0 SLICE_650
ROUTE 2 0.637 R7C6A.F0 to R7C7D.D1 MOD_OBJ_EVAL/m4_4
CTOF_DEL --- 0.495 R7C7D.D1 to R7C7D.F1 MOD_OBJ_EVAL/SLICE_148
ROUTE 1 0.436 R7C7D.F1 to R7C7D.C0 MOD_OBJ_EVAL/N_41_mux
CTOF_DEL --- 0.495 R7C7D.C0 to R7C7D.F0 MOD_OBJ_EVAL/SLICE_148
ROUTE 5 1.205 R7C7D.F0 to R4C6A.D0 MOD_OBJ_EVAL/un1_DO_COPY_i_0
CTOF_DEL --- 0.495 R4C6A.D0 to R4C6A.F0 SLICE_131
ROUTE 4 1.096 R4C6A.F0 to R5C5D.D1 N_45_mux
CTOF_DEL --- 0.495 R5C5D.D1 to R5C5D.F1 SLICE_705
ROUTE 4 0.445 R5C5D.F1 to R5C5D.C0 MOD_OBJ_EVAL/N_26
CTOF_DEL --- 0.495 R5C5D.C0 to R5C5D.F0 SLICE_705
ROUTE 3 0.661 R5C5D.F0 to R5C4A.D1 MOD_OBJ_EVAL/N_29
CTOF_DEL --- 0.495 R5C4A.D1 to R5C4A.F1 SLICE_125
ROUTE 1 0.000 R5C4A.F1 to R5C4A.DI1 N_32_i_0 (to Clk)
--------
13.549 (42.6% logic, 57.4% route), 12 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to SLICE_556:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R9C15B.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to SLICE_125:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R5C4A.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.566ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_READBUSMUX/OB_R[0] (from Clk +)
Destination: FF Data in MOD_OAM/OAMCNT/CNT1[6] (to Clk +)
Delay: 13.549ns (42.6% logic, 57.4% route), 12 logic levels.
Constraint Details:
13.549ns physical path delay SLICE_556 to SLICE_125 meets
23.281ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 23.115ns) by 9.566ns
Physical Path Details:
Data path SLICE_556 to SLICE_125:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R9C15B.CLK to R9C15B.Q1 SLICE_556 (from Clk)
ROUTE 3 1.846 R9C15B.Q1 to R9C8A.B1 MOD_READBUSMUX.OB_R[0]
C1TOFCO_DE --- 0.889 R9C8A.B1 to R9C8A.FCO SLICE_0
ROUTE 1 0.000 R9C8A.FCO to R9C8B.FCI MOD_OBJ_EVAL/OVS_cry_0
FCITOFCO_D --- 0.162 R9C8B.FCI to R9C8B.FCO SLICE_4
ROUTE 1 0.000 R9C8B.FCO to R9C8C.FCI MOD_OBJ_EVAL/OVS_cry_2
FCITOFCO_D --- 0.162 R9C8C.FCI to R9C8C.FCO SLICE_3
ROUTE 1 0.000 R9C8C.FCO to R9C8D.FCI MOD_OBJ_EVAL/OVS_cry_4
FCITOF1_DE --- 0.643 R9C8D.FCI to R9C8D.F1 SLICE_2
ROUTE 1 1.450 R9C8D.F1 to R7C6A.B0 MOD_OBJ_EVAL/OVS[6]
CTOF_DEL --- 0.495 R7C6A.B0 to R7C6A.F0 SLICE_650
ROUTE 2 0.637 R7C6A.F0 to R7C7D.D1 MOD_OBJ_EVAL/m4_4
CTOF_DEL --- 0.495 R7C7D.D1 to R7C7D.F1 MOD_OBJ_EVAL/SLICE_148
ROUTE 1 0.436 R7C7D.F1 to R7C7D.C0 MOD_OBJ_EVAL/N_41_mux
CTOF_DEL --- 0.495 R7C7D.C0 to R7C7D.F0 MOD_OBJ_EVAL/SLICE_148
ROUTE 5 1.205 R7C7D.F0 to R4C6A.D0 MOD_OBJ_EVAL/un1_DO_COPY_i_0
CTOF_DEL --- 0.495 R4C6A.D0 to R4C6A.F0 SLICE_131
ROUTE 4 1.096 R4C6A.F0 to R5C5D.D1 N_45_mux
CTOF_DEL --- 0.495 R5C5D.D1 to R5C5D.F1 SLICE_705
ROUTE 4 0.445 R5C5D.F1 to R5C5D.C0 MOD_OBJ_EVAL/N_26
CTOF_DEL --- 0.495 R5C5D.C0 to R5C5D.F0 SLICE_705
ROUTE 3 0.661 R5C5D.F0 to R5C4A.D0 MOD_OBJ_EVAL/N_29
CTOF_DEL --- 0.495 R5C4A.D0 to R5C4A.F0 SLICE_125
ROUTE 1 0.000 R5C4A.F0 to R5C4A.DI0 N_33_i_0 (to Clk)
--------
13.549 (42.6% logic, 57.4% route), 12 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to SLICE_556:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R9C15B.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to SLICE_125:
Name Fanout Delay (ns) Site Resource
ROUTE 605 1.652 LPLL.CLKOP to R5C4A.CLK Clk
--------
1.652 (0.0% logic, 100.0% route), 0 logic levels.
Report: 71.500MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "MCLK_c" 21.477000 MHz ; | 21.477 MHz| 213.493 MHz| 1
| | |
FREQUENCY NET "Clk" 42.954000 MHz ; | 42.954 MHz| 71.500 MHz| 10
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: MCLK_c Source: MCLK.PAD Loads: 4
Covered under: FREQUENCY NET "MCLK_c" 21.477000 MHz ;
Clock Domain: Clk Source: MOD_PLL/PLLInst_0.CLKOP Loads: 605
Covered under: FREQUENCY NET "Clk" 42.954000 MHz ;
Data transfers from:
Clock Domain: MCLK_c Source: MCLK.PAD
Covered under: FREQUENCY NET "Clk" 42.954000 MHz ; Transfers: 3
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 8033 paths, 2 nets, and 5192 connections (92.45% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond Version 3.5.0.102
Thu Apr 16 21:37:19 2026
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2015 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o PPU_LITE_LATTICE_V3_based.twr -gui -msgset D:/SRC/PPU_LITE_LATTICE_V3/promote.xml PPU_LITE_LATTICE_V3_based.ncd PPU_LITE_LATTICE_V3_based.prf
Design file: ppu_lite_lattice_v3_based.ncd
Preference file: ppu_lite_lattice_v3_based.prf
Device,speed: LCMXO2-1200HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "MCLK_c" 21.477000 MHz (0 errors) 5 items scored, 0 timing errors detected.
FREQUENCY NET "Clk" 42.954000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "MCLK_c" 21.477000 MHz ;
5 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.216ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_CLK_DIV/DIV[2] (from MCLK_c +)
Destination: FF Data in MOD_CLK_DIV/DIV[0] (to MCLK_c +)
Delay: 0.410ns (57.1% logic, 42.9% route), 2 logic levels.
Constraint Details:
0.410ns physical path delay SLICE_89 to MOD_CLK_DIV/SLICE_88 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
-0.207ns skew requirement (totaling 0.194ns) by 0.216ns
Physical Path Details:
Data path SLICE_89 to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R8C12A.CLK to R8C12A.Q0 SLICE_89 (from MCLK_c)
ROUTE 3 0.176 R8C12A.Q0 to R7C12D.D0 MOD_CLK_DIV/DIV[2]
CTOF_DEL --- 0.101 R7C12D.D0 to R7C12D.F0 MOD_CLK_DIV/SLICE_88
ROUTE 1 0.000 R7C12D.F0 to R7C12D.DI0 MOD_CLK_DIV/un2_DIV_i (to MCLK_c)
--------
0.410 (57.1% logic, 42.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path MCLK to SLICE_89:
Name Fanout Delay (ns) Site Resource
ROUTE 4 0.664 34.PADDI to R8C12A.CLK MCLK_c
--------
0.664 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MCLK to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 4 0.871 34.PADDI to R7C12D.CLK MCLK_c
--------
0.871 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.465ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_CLK_DIV/DIV[1] (from MCLK_c +)
Destination: FF Data in MOD_CLK_DIV/DIV[0] (to MCLK_c +)
Delay: 0.452ns (51.8% logic, 48.2% route), 2 logic levels.
Constraint Details:
0.452ns physical path delay MOD_CLK_DIV/SLICE_88 to MOD_CLK_DIV/SLICE_88 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.465ns
Physical Path Details:
Data path MOD_CLK_DIV/SLICE_88 to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C12D.CLK to R7C12D.Q1 MOD_CLK_DIV/SLICE_88 (from MCLK_c)
ROUTE 5 0.218 R7C12D.Q1 to R7C12D.A0 MOD_CLK_DIV/DIV[1]
CTOF_DEL --- 0.101 R7C12D.A0 to R7C12D.F0 MOD_CLK_DIV/SLICE_88
ROUTE 1 0.000 R7C12D.F0 to R7C12D.DI0 MOD_CLK_DIV/un2_DIV_i (to MCLK_c)
--------
0.452 (51.8% logic, 48.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path MCLK to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 4 0.871 34.PADDI to R7C12D.CLK MCLK_c
--------
0.871 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MCLK to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 4 0.871 34.PADDI to R7C12D.CLK MCLK_c
--------
0.871 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.524ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_CLK_DIV/DIV[0] (from MCLK_c +)
Destination: FF Data in MOD_CLK_DIV/DIV[1] (to MCLK_c +)
Delay: 0.505ns (26.3% logic, 73.7% route), 1 logic levels.
Constraint Details:
0.505ns physical path delay MOD_CLK_DIV/SLICE_88 to MOD_CLK_DIV/SLICE_88 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.524ns
Physical Path Details:
Data path MOD_CLK_DIV/SLICE_88 to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C12D.CLK to R7C12D.Q0 MOD_CLK_DIV/SLICE_88 (from MCLK_c)
ROUTE 1 0.372 R7C12D.Q0 to R7C12D.M1 MOD_CLK_DIV/DIV[0] (to MCLK_c)
--------
0.505 (26.3% logic, 73.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path MCLK to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 4 0.871 34.PADDI to R7C12D.CLK MCLK_c
--------
0.871 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MCLK to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 4 0.871 34.PADDI to R7C12D.CLK MCLK_c
--------
0.871 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.684ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_CLK_DIV/DIV[1] (from MCLK_c +)
Destination: FF Data in MOD_CLK_DIV/DIV[2] (to MCLK_c +)
Delay: 0.464ns (50.4% logic, 49.6% route), 2 logic levels.
Constraint Details:
0.464ns physical path delay MOD_CLK_DIV/SLICE_88 to SLICE_89 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.207ns skew requirement (totaling -0.220ns) by 0.684ns
Physical Path Details:
Data path MOD_CLK_DIV/SLICE_88 to SLICE_89:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C12D.CLK to R7C12D.Q1 MOD_CLK_DIV/SLICE_88 (from MCLK_c)
ROUTE 5 0.230 R7C12D.Q1 to R8C12A.B0 MOD_CLK_DIV/DIV[1]
CTOF_DEL --- 0.101 R8C12A.B0 to R8C12A.F0 SLICE_89
ROUTE 1 0.000 R8C12A.F0 to R8C12A.DI0 MOD_CLK_DIV/DIV2n_2 (to MCLK_c)
--------
0.464 (50.4% logic, 49.6% route), 2 logic levels.
Clock Skew Details:
Source Clock Path MCLK to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 4 0.871 34.PADDI to R7C12D.CLK MCLK_c
--------
0.871 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MCLK to SLICE_89:
Name Fanout Delay (ns) Site Resource
ROUTE 4 0.664 34.PADDI to R8C12A.CLK MCLK_c
--------
0.664 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 23.912ns (weighted slack = 47.824ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_CLK_DIV/DIV[1] (from MCLK_c +)
Destination: FF Data in MOD_CLK_DIV/DIV2n (to MCLK_c -)
Delay: 0.405ns (32.8% logic, 67.2% route), 1 logic levels.
Constraint Details:
0.405ns physical path delay MOD_CLK_DIV/SLICE_88 to SLICE_775 meets
-0.019ns M_HLD and
-23.281ns delay constraint less
0.207ns skew requirement (totaling -23.507ns) by 23.912ns
Physical Path Details:
Data path MOD_CLK_DIV/SLICE_88 to SLICE_775:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C12D.CLK to R7C12D.Q1 MOD_CLK_DIV/SLICE_88 (from MCLK_c)
ROUTE 5 0.272 R7C12D.Q1 to R8C12D.M0 MOD_CLK_DIV/DIV[1] (to MCLK_c)
--------
0.405 (32.8% logic, 67.2% route), 1 logic levels.
Clock Skew Details:
Source Clock Path MCLK to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 4 0.871 34.PADDI to R7C12D.CLK MCLK_c
--------
0.871 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MCLK to SLICE_775:
Name Fanout Delay (ns) Site Resource
ROUTE 4 0.664 34.PADDI to R8C12D.CLK MCLK_c
--------
0.664 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
Preference: FREQUENCY NET "Clk" 42.954000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_OBJ_FIFO/SREG_6B/QS_IN[3] (from Clk +)
Destination: FF Data in MOD_OBJ_FIFO/SREG_6B/QP[3] (to Clk +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay MOD_OBJ_FIFO/SREG_6B/SLICE_425 to MOD_OBJ_FIFO/SREG_6B/SLICE_938 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path MOD_OBJ_FIFO/SREG_6B/SLICE_425 to MOD_OBJ_FIFO/SREG_6B/SLICE_938:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C10C.CLK to R2C10C.Q1 MOD_OBJ_FIFO/SREG_6B/SLICE_425 (from Clk)
ROUTE 1 0.152 R2C10C.Q1 to R2C10A.M0 MOD_OBJ_FIFO/SREG_6B/QS_IN[3] (to Clk)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to MOD_OBJ_FIFO/SREG_6B/SLICE_425:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R2C10C.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to MOD_OBJ_FIFO/SREG_6B/SLICE_938:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R2C10A.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_OBJ_FIFO/SREG_6A/QS_IN[7] (from Clk +)
Destination: FF Data in MOD_OBJ_FIFO/SREG_6A/QP[7] (to Clk +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay MOD_OBJ_FIFO/SREG_6A/SLICE_419 to MOD_OBJ_FIFO/SREG_6A/SLICE_192 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path MOD_OBJ_FIFO/SREG_6A/SLICE_419 to MOD_OBJ_FIFO/SREG_6A/SLICE_192:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C14B.CLK to R2C14B.Q1 MOD_OBJ_FIFO/SREG_6A/SLICE_419 (from Clk)
ROUTE 1 0.152 R2C14B.Q1 to R2C14C.M0 MOD_OBJ_FIFO/SREG_6A/QS_IN[7] (to Clk)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to MOD_OBJ_FIFO/SREG_6A/SLICE_419:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R2C14B.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to MOD_OBJ_FIFO/SREG_6A/SLICE_192:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R2C14C.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_OBJ_FIFO/SREG_7A/QS_IN[7] (from Clk +)
Destination: FF Data in MOD_OBJ_FIFO/SREG_7A/QP[7] (to Clk +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay MOD_OBJ_FIFO/SREG_7A/SLICE_435 to MOD_OBJ_FIFO/SREG_7A/SLICE_893 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path MOD_OBJ_FIFO/SREG_7A/SLICE_435 to MOD_OBJ_FIFO/SREG_7A/SLICE_893:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C14A.CLK to R2C14A.Q1 MOD_OBJ_FIFO/SREG_7A/SLICE_435 (from Clk)
ROUTE 1 0.152 R2C14A.Q1 to R2C14D.M0 MOD_OBJ_FIFO/SREG_7A/QS_IN[7] (to Clk)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to MOD_OBJ_FIFO/SREG_7A/SLICE_435:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R2C14A.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to MOD_OBJ_FIFO/SREG_7A/SLICE_893:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R2C14D.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_OBJ_FIFO/SREG_4A/QS_IN[1] (from Clk +)
Destination: FF Data in MOD_OBJ_FIFO/SREG_4A/QP[1] (to Clk +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay MOD_OBJ_FIFO/SREG_4A/SLICE_384 to MOD_OBJ_FIFO/SREG_4A/SLICE_922 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path MOD_OBJ_FIFO/SREG_4A/SLICE_384 to MOD_OBJ_FIFO/SREG_4A/SLICE_922:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C18C.CLK to R2C18C.Q1 MOD_OBJ_FIFO/SREG_4A/SLICE_384 (from Clk)
ROUTE 1 0.152 R2C18C.Q1 to R2C18D.M0 MOD_OBJ_FIFO/SREG_4A/QS_IN[1] (to Clk)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to MOD_OBJ_FIFO/SREG_4A/SLICE_384:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R2C18C.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to MOD_OBJ_FIFO/SREG_4A/SLICE_922:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R2C18D.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_OBJ_FIFO/SREG_5A/QS_IN[5] (from Clk +)
Destination: FF Data in MOD_OBJ_FIFO/SREG_5A/QP[5] (to Clk +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay MOD_OBJ_FIFO/SREG_5A/SLICE_402 to MOD_OBJ_FIFO/SREG_5A/SLICE_930 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path MOD_OBJ_FIFO/SREG_5A/SLICE_402 to MOD_OBJ_FIFO/SREG_5A/SLICE_930:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C12C.CLK to R3C12C.Q1 MOD_OBJ_FIFO/SREG_5A/SLICE_402 (from Clk)
ROUTE 1 0.152 R3C12C.Q1 to R3C12B.M0 MOD_OBJ_FIFO/SREG_5A/QS_IN[5] (to Clk)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to MOD_OBJ_FIFO/SREG_5A/SLICE_402:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R3C12C.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to MOD_OBJ_FIFO/SREG_5A/SLICE_930:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R3C12B.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_OBJ_FIFO/SREG_5B/QS_IN[5] (from Clk +)
Destination: FF Data in MOD_OBJ_FIFO/SREG_5B/QP[5] (to Clk +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay MOD_OBJ_FIFO/SREG_5B/SLICE_410 to MOD_OBJ_FIFO/SREG_5B/SLICE_933 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path MOD_OBJ_FIFO/SREG_5B/SLICE_410 to MOD_OBJ_FIFO/SREG_5B/SLICE_933:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C7B.CLK to R2C7B.Q1 MOD_OBJ_FIFO/SREG_5B/SLICE_410 (from Clk)
ROUTE 1 0.152 R2C7B.Q1 to R2C7A.M0 MOD_OBJ_FIFO/SREG_5B/QS_IN[5] (to Clk)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to MOD_OBJ_FIFO/SREG_5B/SLICE_410:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R2C7B.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to MOD_OBJ_FIFO/SREG_5B/SLICE_933:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R2C7A.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_OBJ_FIFO/SREG_4B/QS_IN[3] (from Clk +)
Destination: FF Data in MOD_OBJ_FIFO/SREG_4B/QP[3] (to Clk +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay MOD_OBJ_FIFO/SREG_4B/SLICE_393 to MOD_OBJ_FIFO/SREG_4B/SLICE_926 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path MOD_OBJ_FIFO/SREG_4B/SLICE_393 to MOD_OBJ_FIFO/SREG_4B/SLICE_926:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C16B.CLK to R4C16B.Q1 MOD_OBJ_FIFO/SREG_4B/SLICE_393 (from Clk)
ROUTE 1 0.152 R4C16B.Q1 to R4C16D.M0 MOD_OBJ_FIFO/SREG_4B/QS_IN[3] (to Clk)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to MOD_OBJ_FIFO/SREG_4B/SLICE_393:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R4C16B.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to MOD_OBJ_FIFO/SREG_4B/SLICE_926:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R4C16D.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_OBJ_FIFO/ATR_IN0[0] (from Clk +)
Destination: FF Data in MOD_OBJ_FIFO/ATR0[0] (to Clk +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay MOD_OBJ_FIFO/SLICE_770 to SLICE_794 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path MOD_OBJ_FIFO/SLICE_770 to SLICE_794:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C18A.CLK to R7C18A.Q0 MOD_OBJ_FIFO/SLICE_770 (from Clk)
ROUTE 1 0.152 R7C18A.Q0 to R7C18B.M0 MOD_OBJ_FIFO/ATR_IN0[0] (to Clk)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to MOD_OBJ_FIFO/SLICE_770:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R7C18A.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to SLICE_794:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R7C18B.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_OBJ_FIFO/SREG_0A/QS_IN[6] (from Clk +)
Destination: FF Data in MOD_OBJ_FIFO/SREG_0A/QP[6] (to Clk +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay MOD_OBJ_FIFO/SREG_0A/SLICE_323 to SLICE_761 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path MOD_OBJ_FIFO/SREG_0A/SLICE_323 to SLICE_761:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C11B.CLK to R5C11B.Q0 MOD_OBJ_FIFO/SREG_0A/SLICE_323 (from Clk)
ROUTE 1 0.152 R5C11B.Q0 to R5C11D.M1 MOD_OBJ_FIFO/SREG_0A/QS_IN[6] (to Clk)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to MOD_OBJ_FIFO/SREG_0A/SLICE_323:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R5C11B.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to SLICE_761:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R5C11D.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_OBJ_FIFO/SREG_5A/QS_IN[7] (from Clk +)
Destination: FF Data in MOD_OBJ_FIFO/SREG_5A/QP[7] (to Clk +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay MOD_OBJ_FIFO/SREG_5A/SLICE_403 to MOD_OBJ_FIFO/SREG_5A/SLICE_892 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path MOD_OBJ_FIFO/SREG_5A/SLICE_403 to MOD_OBJ_FIFO/SREG_5A/SLICE_892:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C11C.CLK to R3C11C.Q1 MOD_OBJ_FIFO/SREG_5A/SLICE_403 (from Clk)
ROUTE 1 0.152 R3C11C.Q1 to R3C11A.M0 MOD_OBJ_FIFO/SREG_5A/QS_IN[7] (to Clk)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path MOD_PLL/PLLInst_0 to MOD_OBJ_FIFO/SREG_5A/SLICE_403:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R3C11C.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path MOD_PLL/PLLInst_0 to MOD_OBJ_FIFO/SREG_5A/SLICE_892:
Name Fanout Delay (ns) Site Resource
ROUTE 605 0.595 LPLL.CLKOP to R3C11A.CLK Clk
--------
0.595 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
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Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "MCLK_c" 21.477000 MHz ; | 0.000 ns| 0.216 ns| 2
| | |
FREQUENCY NET "Clk" 42.954000 MHz ; | 0.000 ns| 0.304 ns| 1
| | |
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All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: MCLK_c Source: MCLK.PAD Loads: 4
Covered under: FREQUENCY NET "MCLK_c" 21.477000 MHz ;
Clock Domain: Clk Source: MOD_PLL/PLLInst_0.CLKOP Loads: 605
Covered under: FREQUENCY NET "Clk" 42.954000 MHz ;
Data transfers from:
Clock Domain: MCLK_c Source: MCLK.PAD
Covered under: FREQUENCY NET "Clk" 42.954000 MHz ; Transfers: 3
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 8033 paths, 2 nets, and 5192 connections (92.45% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
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