Map TRACE Report
Loading design for application trce from file ppu_lite_lattice_v3_based_map.ncd.
Design name: RP2C02_LITE_LAT_V3
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.5/ispfpga.
Package Status: Final Version 1.41.
Performance Hardware Data Status: Final Version 30.4.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond Version 3.5.0.102
Thu Apr 16 21:36:55 2026
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2015 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o PPU_LITE_LATTICE_V3_based.tw1 -gui -msgset D:/SRC/PPU_LITE_LATTICE_V3/promote.xml PPU_LITE_LATTICE_V3_based_map.ncd PPU_LITE_LATTICE_V3_based.prf
Design file: ppu_lite_lattice_v3_based_map.ncd
Preference file: ppu_lite_lattice_v3_based.prf
Device,speed: LCMXO2-1200HC,4
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "MCLK_c" 21.477000 MHz (0 errors) 5 items scored, 0 timing errors detected.
Report: 245.942MHz is the maximum frequency for this preference.
FREQUENCY NET "Clk" 42.954000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
Report: 69.896MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "MCLK_c" 21.477000 MHz ;
5 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 21.247ns (weighted slack = 42.494ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_CLK_DIV/DIV[1] (from MCLK_c +)
Destination: FF Data in MOD_CLK_DIV/DIV2n (to MCLK_c -)
Delay: 1.686ns (26.8% logic, 73.2% route), 1 logic levels.
Constraint Details:
1.686ns physical path delay MOD_CLK_DIV/SLICE_88 to SLICE_775 meets
23.281ns delay constraint less
0.348ns M_SET requirement (totaling 22.933ns) by 21.247ns
Physical Path Details:
Data path MOD_CLK_DIV/SLICE_88 to SLICE_775:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 */SLICE_88.CLK to *V/SLICE_88.Q1 MOD_CLK_DIV/SLICE_88 (from MCLK_c)
ROUTE 5 e 1.234 *V/SLICE_88.Q1 to SLICE_775.M0 MOD_CLK_DIV/DIV[1] (to MCLK_c)
--------
1.686 (26.8% logic, 73.2% route), 1 logic levels.
Report: 245.942MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "Clk" 42.954000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 8.974ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_TIMING_GENERATOR/VCNT[0]/CNT (from Clk +)
Destination: FF Data in MOD_OAM/OAMCNT/CNT1[5] (to Clk +)
Delay: 14.141ns (40.8% logic, 59.2% route), 12 logic levels.
Constraint Details:
14.141ns physical path delay MOD_TIMING_GENERATOR/SLICE_652 to SLICE_124 meets
23.281ns delay constraint less
0.166ns DIN_SET requirement (totaling 23.115ns) by 8.974ns
Physical Path Details:
Data path MOD_TIMING_GENERATOR/SLICE_652 to SLICE_124:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 *SLICE_652.CLK to */SLICE_652.Q0 MOD_TIMING_GENERATOR/SLICE_652 (from Clk)
ROUTE 14 e 1.234 */SLICE_652.Q0 to SLICE_0.A1 Vo[0]
C1TOFCO_DE --- 0.889 SLICE_0.A1 to SLICE_0.FCO SLICE_0
ROUTE 1 e 0.001 SLICE_0.FCO to SLICE_4.FCI MOD_OBJ_EVAL/OVS_cry_0
FCITOFCO_D --- 0.162 SLICE_4.FCI to SLICE_4.FCO SLICE_4
ROUTE 1 e 0.001 SLICE_4.FCO to SLICE_3.FCI MOD_OBJ_EVAL/OVS_cry_2
FCITOFCO_D --- 0.162 SLICE_3.FCI to SLICE_3.FCO SLICE_3
ROUTE 1 e 0.001 SLICE_3.FCO to SLICE_2.FCI MOD_OBJ_EVAL/OVS_cry_4
FCITOF1_DE --- 0.643 SLICE_2.FCI to SLICE_2.F1 SLICE_2
ROUTE 1 e 1.234 SLICE_2.F1 to SLICE_650.B0 MOD_OBJ_EVAL/OVS[6]
CTOF_DEL --- 0.495 SLICE_650.B0 to SLICE_650.F0 SLICE_650
ROUTE 2 e 1.234 SLICE_650.F0 to */SLICE_148.D1 MOD_OBJ_EVAL/m4_4
CTOF_DEL --- 0.495 */SLICE_148.D1 to */SLICE_148.F1 MOD_OBJ_EVAL/SLICE_148
ROUTE 1 e 0.480 */SLICE_148.F1 to */SLICE_148.B0 MOD_OBJ_EVAL/N_41_mux
CTOF_DEL --- 0.495 */SLICE_148.B0 to */SLICE_148.F0 MOD_OBJ_EVAL/SLICE_148
ROUTE 5 e 1.234 */SLICE_148.F0 to SLICE_131.A0 MOD_OBJ_EVAL/un1_DO_COPY_i_0
CTOF_DEL --- 0.495 SLICE_131.A0 to SLICE_131.F0 SLICE_131
ROUTE 4 e 1.234 SLICE_131.F0 to SLICE_705.C1 N_45_mux
CTOF_DEL --- 0.495 SLICE_705.C1 to SLICE_705.F1 SLICE_705
ROUTE 4 e 0.480 SLICE_705.F1 to SLICE_705.D0 MOD_OBJ_EVAL/N_26
CTOF_DEL --- 0.495 SLICE_705.D0 to SLICE_705.F0 SLICE_705
ROUTE 3 e 1.234 SLICE_705.F0 to SLICE_124.B1 MOD_OBJ_EVAL/N_29
CTOF_DEL --- 0.495 SLICE_124.B1 to SLICE_124.F1 SLICE_124
ROUTE 1 e 0.001 SLICE_124.F1 to SLICE_124.DI1 N_34_i_0 (to Clk)
--------
14.141 (40.8% logic, 59.2% route), 12 logic levels.
Report: 69.896MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "MCLK_c" 21.477000 MHz ; | 21.477 MHz| 245.942 MHz| 1
| | |
FREQUENCY NET "Clk" 42.954000 MHz ; | 42.954 MHz| 69.896 MHz| 12
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: Clk Source: MOD_PLL/PLLInst_0.CLKOP Loads: 605
Covered under: FREQUENCY NET "Clk" 42.954000 MHz ;
Data transfers from:
Clock Domain: MCLK_c Source: MCLK.PAD
Covered under: FREQUENCY NET "Clk" 42.954000 MHz ; Transfers: 3
Clock Domain: MCLK_c Source: MCLK.PAD Loads: 4
Covered under: FREQUENCY NET "MCLK_c" 21.477000 MHz ;
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 8033 paths, 2 nets, and 5054 connections (89.99% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond Version 3.5.0.102
Thu Apr 16 21:36:56 2026
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2015 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o PPU_LITE_LATTICE_V3_based.tw1 -gui -msgset D:/SRC/PPU_LITE_LATTICE_V3/promote.xml PPU_LITE_LATTICE_V3_based_map.ncd PPU_LITE_LATTICE_V3_based.prf
Design file: ppu_lite_lattice_v3_based_map.ncd
Preference file: ppu_lite_lattice_v3_based.prf
Device,speed: LCMXO2-1200HC,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "MCLK_c" 21.477000 MHz (0 errors) 5 items scored, 0 timing errors detected.
FREQUENCY NET "Clk" 42.954000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "MCLK_c" 21.477000 MHz ;
5 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.351ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_CLK_DIV/DIV[0] (from MCLK_c +)
Destination: FF Data in MOD_CLK_DIV/DIV[1] (to MCLK_c +)
Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
Constraint Details:
0.332ns physical path delay MOD_CLK_DIV/SLICE_88 to MOD_CLK_DIV/SLICE_88 meets
-0.019ns M_HLD and
0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
Physical Path Details:
Data path MOD_CLK_DIV/SLICE_88 to MOD_CLK_DIV/SLICE_88:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 */SLICE_88.CLK to *V/SLICE_88.Q0 MOD_CLK_DIV/SLICE_88 (from MCLK_c)
ROUTE 1 e 0.199 *V/SLICE_88.Q0 to *V/SLICE_88.M1 MOD_CLK_DIV/DIV[0] (to MCLK_c)
--------
0.332 (40.1% logic, 59.9% route), 1 logic levels.
================================================================================
Preference: FREQUENCY NET "Clk" 42.954000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.351ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q MOD_PALETTE/PICTR[1] (from Clk +)
Destination: FF Data in MOD_PALETTE/PICTR[2] (to Clk +)
Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
Constraint Details:
0.332ns physical path delay MOD_PALETTE/SLICE_789 to MOD_PALETTE/SLICE_789 meets
-0.019ns M_HLD and
0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
Physical Path Details:
Data path MOD_PALETTE/SLICE_789 to MOD_PALETTE/SLICE_789:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 *SLICE_789.CLK to */SLICE_789.Q0 MOD_PALETTE/SLICE_789 (from Clk)
ROUTE 1 e 0.199 */SLICE_789.Q0 to */SLICE_789.M1 MOD_PALETTE/PICTR[1] (to Clk)
--------
0.332 (40.1% logic, 59.9% route), 1 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "MCLK_c" 21.477000 MHz ; | 0.000 ns| 0.351 ns| 1
| | |
FREQUENCY NET "Clk" 42.954000 MHz ; | 0.000 ns| 0.351 ns| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: Clk Source: MOD_PLL/PLLInst_0.CLKOP Loads: 605
Covered under: FREQUENCY NET "Clk" 42.954000 MHz ;
Data transfers from:
Clock Domain: MCLK_c Source: MCLK.PAD
Covered under: FREQUENCY NET "Clk" 42.954000 MHz ; Transfers: 3
Clock Domain: MCLK_c Source: MCLK.PAD Loads: 4
Covered under: FREQUENCY NET "MCLK_c" 21.477000 MHz ;
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 8033 paths, 2 nets, and 5192 connections (92.45% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------