PAR: Place And Route Diamond Version 3.5.0.102.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2015 Lattice Semiconductor Corporation, All rights reserved.
Thu Apr 16 21:36:56 2026
C:/lscc/diamond/3.5/ispfpga\bin\nt\par -f PPU_LITE_LATTICE_V3_based.p2t
PPU_LITE_LATTICE_V3_based_map.ncd PPU_LITE_LATTICE_V3_based.dir
PPU_LITE_LATTICE_V3_based.prf -gui -msgset
D:/SRC/PPU_LITE_LATTICE_V3/promote.xml
Preference file: PPU_LITE_LATTICE_V3_based.prf.
Cost Table Summary
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ----- ------
5_1 * 0 9.295 0 0.216 0 22 Complete
* : Design saved.
Total (real) run time for 1-seed: 22 secs
par done!
Lattice Place and Route Report for Design "PPU_LITE_LATTICE_V3_based_map.ncd"
Thu Apr 16 21:36:56 2026
Best Par Run
PAR: Place And Route Diamond Version 3.5.0.102.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/SRC/PPU_LITE_LATTICE_V3/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF PPU_LITE_LATTICE_V3_based_map.ncd PPU_LITE_LATTICE_V3_based.dir/5_1.ncd PPU_LITE_LATTICE_V3_based.prf
Preference file: PPU_LITE_LATTICE_V3_based.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file PPU_LITE_LATTICE_V3_based_map.ncd.
Design name: RP2C02_LITE_LAT_V3
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.5/ispfpga.
Package Status: Final Version 1.41.
Performance Hardware Data Status: Final Version 30.4.
License checked out.
Ignore Preference Error(s): True
Device utilization summary:
PIO (prelim) 69+4(JTAG)/108 68% used
69+4(JTAG)/80 91% bonded
IOLOGIC 21/108 19% used
SLICE 591/640 92% used
GSR 1/1 100% used
EBR 4/7 57% used
PLL 1/1 100% used
INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
Number of Signals: 2073
Number of Connections: 5616
Pin Constraint Summary:
69 out of 69 pins locked (100% locked).
The following 1 signal is selected to use the primary clock routing resources:
Clk (driver: MOD_PLL/PLLInst_0, clk load #: 604)
The following 4 signals are selected to use the secondary clock routing resources:
PCLK_i (driver: MOD_CLK_DIV/SLICE_88, clk load #: 0, sr load #: 0, ce load #: 155)
PCLK_0 (driver: SLICE_680, clk load #: 0, sr load #: 0, ce load #: 101)
MOD_BG_COLOR/STEP2 (driver: SLICE_806, clk load #: 0, sr load #: 0, ce load #: 24)
MOD_OBJ_EVAL.un1_nPCLK_i (driver: SLICE_809, clk load #: 0, sr load #: 0, ce load #: 11)
Signal MOD_OAM/un1_ORES_i is selected as Global Set/Reset.
Starting Placer Phase 0.
.........
Finished Placer Phase 0. REAL time: 2 secs
Starting Placer Phase 1.
.....................
Placer score = 307178.
Finished Placer Phase 1. REAL time: 10 secs
Starting Placer Phase 2.
.
Placer score = 305857
Finished Placer Phase 2. REAL time: 11 secs
Clock Report
Global Clock Resources:
CLK_PIN : 0 out of 8 (0%)
PLL : 1 out of 1 (100%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Quadrants All (TL, TR, BL, BR) - Global Clocks:
PRIMARY "Clk" from CLKOP on comp "MOD_PLL/PLLInst_0" on PLL site "LPLL", clk load = 604
SECONDARY "PCLK_i" from F1 on comp "MOD_CLK_DIV/SLICE_88" on site "R7C12D", clk load = 0, ce load = 155, sr load = 0
SECONDARY "PCLK_0" from F1 on comp "SLICE_680" on site "R7C12A", clk load = 0, ce load = 101, sr load = 0
SECONDARY "MOD_BG_COLOR/STEP2" from F1 on comp "SLICE_806" on site "R7C14B", clk load = 0, ce load = 24, sr load = 0
SECONDARY "MOD_OBJ_EVAL.un1_nPCLK_i" from F0 on comp "SLICE_809" on site "R7C12B", clk load = 0, ce load = 11, sr load = 0
PRIMARY : 1 out of 8 (12%)
SECONDARY: 4 out of 8 (50%)
Edge Clocks:
No edge clock selected.
I/O Usage Summary (final):
69 + 4(JTAG) out of 108 (67.6%) PIO sites used.
69 + 4(JTAG) out of 80 (91.3%) bonded PIO sites used.
Number of PIO comps: 69; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 15 / 19 ( 78%) | 3.3V | - |
| 1 | 21 / 21 (100%) | 3.3V | - |
| 2 | 15 / 20 ( 75%) | 3.3V | - |
| 3 | 18 / 20 ( 90%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 10 secs
Dumping design to file PPU_LITE_LATTICE_V3_based.dir/5_1.ncd.
0 connections routed; 5616 unrouted.
Starting router resource preassignment
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=MCLK_c loads=4 clock_loads=4
Completed router resource preassignment. Real time: 12 secs
Start NBR router at 21:37:09 04/16/26
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 21:37:09 04/16/26
Start NBR section for initial routing at 21:37:10 04/16/26
Level 1, iteration 1
0(0.00%) conflict; 4101(73.02%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 9.239ns/0.000ns; real time: 14 secs
Level 2, iteration 1
0(0.00%) conflict; 4099(72.99%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 9.483ns/0.000ns; real time: 14 secs
Level 3, iteration 1
0(0.00%) conflict; 4098(72.97%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 9.616ns/0.000ns; real time: 15 secs
Level 4, iteration 1
126(0.15%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 9.463ns/0.000ns; real time: 16 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 21:37:12 04/16/26
Level 4, iteration 1
64(0.08%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 9.295ns/0.000ns; real time: 16 secs
Level 4, iteration 2
33(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 9.295ns/0.000ns; real time: 17 secs
Level 4, iteration 3
11(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 9.295ns/0.000ns; real time: 17 secs
Level 4, iteration 4
2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 9.295ns/0.000ns; real time: 17 secs
Level 4, iteration 5
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 9.295ns/0.000ns; real time: 18 secs
Level 4, iteration 6
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 9.295ns/0.000ns; real time: 18 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 21:37:14 04/16/26
Start NBR section for re-routing at 21:37:14 04/16/26
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 9.295ns/0.000ns; real time: 18 secs
Start NBR section for post-routing at 21:37:14 04/16/26
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack<setup> : 9.295ns
Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=MCLK_c loads=4 clock_loads=4
Total CPU time 19 secs
Total REAL time: 21 secs
Completely routed.
End of route. 5616 routed (100.00%); 0 unrouted.
Checking DRC ...
No errors found.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file PPU_LITE_LATTICE_V3_based.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = 9.295
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.216
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 20 secs
Total REAL time to completion: 22 secs
par done!
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2015 Lattice Semiconductor Corporation, All rights reserved.