I/O Timing Report Loading design for application iotiming from file ppu_lite_lattice_v3_based.ncd. Design name: RP2C02_LITE_LAT_V3 NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-1200HC Package: TQFP100 Performance: 5 Package Status: Final Version 1.41. Performance Hardware Data Status: Final Version 30.4. Loading design for application iotiming from file ppu_lite_lattice_v3_based.ncd. Design name: RP2C02_LITE_LAT_V3 NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-1200HC Package: TQFP100 Performance: 6 Package Status: Final Version 1.41. Performance Hardware Data Status: Final Version 30.4. Loading design for application iotiming from file ppu_lite_lattice_v3_based.ncd. Design name: RP2C02_LITE_LAT_V3 NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-1200HC Package: TQFP100 Performance: M Package Status: Final Version 1.41. Performance Hardware Data Status: Final Version 30.4. // Design: RP2C02_LITE_LAT_V3 // Package: TQFP100 // ncd File: ppu_lite_lattice_v3_based.ncd // Version: Diamond Version 3.5.0.102 // Written on Thu Apr 16 21:37:23 2026 // M: Minimum Performance Grade // iotiming PPU_LITE_LATTICE_V3_based.ncd PPU_LITE_LATTICE_V3_based.prf -gui -msgset D:/SRC/PPU_LITE_LATTICE_V3/promote.xml I/O Timing Report (All units are in ns) Worst Case Results across Performance Grades (M, 6, 5, 4): // Input Setup and Hold Times Port Clock Edge Setup Performance_Grade Hold Performance_Grade ---------------------------------------------------------------------- A[0] MCLK R 0.462 4 0.667 4 A[1] MCLK R 0.462 4 0.667 4 A[2] MCLK R 0.462 4 0.667 4 DB[0] MCLK R 0.376 4 0.739 4 DB[1] MCLK R 0.376 4 0.739 4 DB[2] MCLK R 0.376 4 0.739 4 DB[3] MCLK R 0.376 4 0.739 4 DB[4] MCLK R 0.376 4 0.739 4 DB[5] MCLK R 0.376 4 0.739 4 DB[6] MCLK R 0.376 4 0.739 4 DB[7] MCLK R 0.462 4 0.667 4 DENDY_IN MCLK R 14.192 4 -0.249 M MODE_IN MCLK R 15.661 4 -0.073 M PALSEL0 MCLK R 1.968 4 -0.205 M PALSEL1 MCLK R 2.185 4 -0.205 M PALSEL2 MCLK R 2.394 4 -0.430 M PD[0] MCLK R 4.696 4 0.720 4 PD[1] MCLK R 3.913 4 0.720 4 PD[2] MCLK R 4.195 4 0.720 4 PD[3] MCLK R 2.907 4 0.720 4 PD[4] MCLK R 3.904 4 0.720 4 PD[5] MCLK R 3.969 4 0.720 4 PD[6] MCLK R 3.508 4 0.720 4 PD[7] MCLK R 3.350 4 0.720 4 RnW MCLK R 4.203 4 0.739 4 nDBE MCLK R 3.581 4 0.720 4 // Clock to Output Delay Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------ ALE MCLK R 17.974 4 2.701 M COMPOSIT[0] MCLK R 20.425 4 3.046 M COMPOSIT[1] MCLK R 18.526 4 2.759 M COMPOSIT[2] MCLK R 18.923 4 2.976 M COMPOSIT[3] MCLK R 17.503 4 2.726 M COMPOSIT[4] MCLK R 19.460 4 2.934 M COMPOSIT[5] MCLK R 17.083 4 2.588 M COMPOSIT[6] MCLK R 18.882 4 2.848 M DB[0] MCLK R 12.332 4 2.772 M DB[1] MCLK R 11.856 4 2.822 M DB[2] MCLK R 11.714 4 2.564 M DB[3] MCLK R 11.478 4 2.556 M DB[4] MCLK R 11.712 4 2.499 M DB[5] MCLK R 12.005 4 2.341 M DB[6] MCLK R 12.583 4 2.568 M DB[7] MCLK R 12.124 4 2.696 M HSYNC MCLK R 6.297 4 2.042 M INT MCLK R 8.907 4 2.557 M PA10 MCLK R 7.314 4 2.284 M PA11 MCLK R 7.386 4 2.319 M PA12 MCLK R 6.871 4 2.175 M PA13 MCLK R 7.242 4 2.249 M PA8 MCLK R 7.673 4 2.395 M PA9 MCLK R 6.896 4 2.182 M PD[0] MCLK R 14.722 4 2.372 M PD[1] MCLK R 14.722 4 2.285 M PD[2] MCLK R 15.576 4 2.040 M PD[3] MCLK R 15.576 4 2.180 M PD[4] MCLK R 14.251 4 2.202 M PD[5] MCLK R 14.251 4 2.121 M PD[6] MCLK R 14.251 4 2.121 M PD[7] MCLK R 14.251 4 2.091 M PD_DIR MCLK R 12.825 4 2.583 M RGB[0] MCLK R 10.296 4 2.436 M RGB[10] MCLK R 10.097 4 2.509 M RGB[11] MCLK R 9.399 4 2.438 M RGB[12] MCLK R 9.123 4 2.445 M RGB[13] MCLK R 9.160 4 2.448 M RGB[14] MCLK R 9.751 4 2.546 M RGB[15] MCLK R 9.781 4 2.518 M RGB[16] MCLK R 9.611 4 2.435 M RGB[17] MCLK R 9.354 4 2.435 M RGB[1] MCLK R 10.411 4 2.436 M RGB[2] MCLK R 9.912 4 2.466 M RGB[3] MCLK R 9.881 4 2.407 M RGB[4] MCLK R 10.081 4 2.554 M RGB[5] MCLK R 10.169 4 2.675 M RGB[6] MCLK R 9.056 4 2.377 M RGB[7] MCLK R 10.083 4 2.572 M RGB[8] MCLK R 8.982 4 2.337 M RGB[9] MCLK R 9.201 4 2.337 M SYNC MCLK R 10.788 4 3.117 M VSYNC MCLK R 7.585 4 2.361 M nRD MCLK R 12.151 4 2.404 M nWR MCLK R 12.264 4 2.799 M WARNING: you must also run trce with hold speed: 4